Patents by Inventor Gerald Lackner

Gerald Lackner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848237
    Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: December 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Publication number: 20230330769
    Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko David Swoboda
  • Patent number: 11712749
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Publication number: 20230170233
    Abstract: In an embodiment a method includes placing a wafer on a receptacle comprising a chuck base, wherein a light port for emitting light from a source of light is an opening located in a surface of the chuck base, and wherein the light port is located underneath the wafer, shining the light from the light port at an edge of the wafer so that light passes by the edge of the wafer and processing the wafer on the receptacle based on the light that passed by the edge of the wafer and that is received by a light sensitive element.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Patent number: 11637028
    Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 25, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Publication number: 20230098233
    Abstract: A chuck for a laser beam wafer dicing equipment includes a wafer support plate having an upper surface for holding a wafer disposed on a dicing tape. The upper surface includes a topographically structured surface region that partly or completely overlaps an edge of the wafer when the wafer disposed on the dicing tape is placed on the upper surface. The topographically structured surface region provides for a reduction in an area of contact between the upper surface and the dicing tape.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 30, 2023
    Inventors: Franz-Josef Pichler, Johannes Mueller, Christoph Ahamer, Gerald Lackner, Walter Leitgeb
  • Publication number: 20230100613
    Abstract: A chuck for a laser beam wafer dicing equipment includes a wafer support plate having an upper surface for holding a wafer disposed on a dicing tape. The upper surface includes an annular groove that overlaps an edge of the wafer when the wafer disposed on the dicing tape is placed on the upper surface. The wafer support plate includes a ventilation channel configured to ventilate the annular groove.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 30, 2023
    Inventors: Franz-Josef Pichler, Johannes Mueller, Christoph Ahamer, Gerald Lackner, Walter Horst Leitgeb
  • Publication number: 20220181211
    Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 11302579
    Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Publication number: 20210217640
    Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.
    Type: Application
    Filed: March 31, 2021
    Publication date: July 15, 2021
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Patent number: 10985041
    Abstract: A method and apparatus for use in a wafer processing are disclosed. In an embodiment a includes providing the wafer on a receptacle, wherein the receptacle comprises a light port, and wherein the light port includes a source of light, shining a light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer and processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Publication number: 20210053148
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 25, 2021
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Patent number: 10777444
    Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 15, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Gerald Lackner, Josef Unterweger
  • Publication number: 20200273750
    Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 10672664
    Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Publication number: 20190122909
    Abstract: A method and apparatus for use in a wafer processing are disclosed. In an embodiment a includes providing the wafer on a receptacle, wherein the receptacle comprises a light port, and wherein the light port includes a source of light, shining a light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer and processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 25, 2019
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Publication number: 20190088550
    Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.
    Type: Application
    Filed: February 27, 2017
    Publication date: March 21, 2019
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 10186438
    Abstract: A method and an apparatus for use in processing a wafer are disclosed. In an embodiment the method includes providing a wafer on a receptacle, shining a light at an edge of the wafer and based on light that passed the edge of the wafer, processing the wafer on the receptacle.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Fischer, Gerald Lackner, Walter Horst Leitgeb, Michael Lecher
  • Publication number: 20180261487
    Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.
    Type: Application
    Filed: April 12, 2018
    Publication date: September 13, 2018
    Inventors: Francisco Javier SANTOS RODRIGUEZ, Gerald LACKNER, Josef UNTERWEGER
  • Patent number: 9966293
    Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably attachable to one another.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 8, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Gerald Lackner, Josef Unterweger