Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.

Abstract: A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.

Abstract: The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semiconductor devices.

Abstract: The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semiconductor devices.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.