Abstract: Embodiments herein relate to a semiconductor package or a semiconductor package structure that includes an interposer with opposing first and second sides. A memory and a processing unit may be coupled with the second side of the interposer, and the first side of the interposer may be to couple with the substrate. The processing unit and memory may be communicatively coupled with one another and the substrate by the interposer. Other embodiments may be described or claimed.

Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that ?k/n? hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that [k/n] hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.