Abstract: A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. As each task in a scenario is executed, a control word associated with the task can be used to enable/disable circuitry, or to set circuits to an optimum configuration.

Abstract: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Abstract: A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.

Abstract: An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.

Abstract: A cache memory architecture 50, which may be, for example, a set associative cache memory, has a cache controller (52) with an internal register for storing the address of the active line currently latched in the output buffer of the high speed cache data array (56) which stores the cached data values from the main memory. If a memory access request specifies an address which would be contained in the active line, the cache look-up mechanisms are disabled and the data is taken from the output buffer. The efficiency of the cache can be increased by linking a program to memory such that the number of cache lines used by one or more program loops are minimized.

Abstract: A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC13 Bn13 ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory.

Abstract: A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: This devise comprising a digital signal processor (1) proper, a ROM program memory (2) and a RAM data memory (3) which are connected respectively to the processor, is characterized in that associated with the RAM data memory is a RAM viterbi memory (7) including means for executing addition, comparison and selection operations of the Viterbi algorithm, and logic (8) for controlling the Viterbi memory (7).

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. This configuration permits the processor to achieve a higher data input rate.

Abstract: An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver devices, and interconnection means (17) for connecting the array of input buses to the array of output buses.

Abstract: Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.

Abstract: Interconnection-pin memory comprising an array of dual-port switching memories used as first-in, first-out devices, characterized in that each dual-port memory (3, 4) of the memory array includes a write-only port (15, 23) and a read-only port (18, 19, 20, 21) having separate address and control signals.

Abstract: A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. The processor (10) is programmable, which makes it especially useful for digital filtering. Near-neighbor communications (41) among processing elements (20) realize the delays required for horizontal filtering.

Abstract: A device including a screen memory (53) for storing the data relating to the points of a screen on which the curve is to be drawn. A point processor (21) modifies the data stored in the screen memory (53) at the positions of said screen memory corresponding to the points of the curve to be drawn. An address processor (20) adapted to control the access to the screen memory (53), the operation of the processor (21) and the transfers of data between the point processor (21) and the screen memory (53) so as to ensure the modification of its content as a function of the line to be drawn. A CROM memory (22) containing instructions relating to the changing of the reference of U, V relative coordinates of each octant change and instructions relating to the point by point drawings of portions of curves contained in each of the octants covered by the arc of a curve to be drawn.

Abstract: A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. This configuration is especially useful for scan rate conversion, where the data output rate may not necessarily be the same as the data input rate.

Abstract: Device for processing telephonic signals for putting in communication a plurality of subscribers by means of a telephone exchange employing circuits on cards of subscribers, comprising digital signal processing devices adapted to create filtering functions for the purpose of connecting the subscribers to one another, characterized in that it comprises, associated with said telephone exchange, at least two digital signal processing devices (15, 16) common to a plurality of lines of subscribers (10a-10n, 11a-11n), each connected, on one hand, to the telephone exchange (17) and, on the other hand, to a group of lines of subscribers and adapted to process the signals coming from said corresponding groups of lines of subscribers in shared time so as to effect calculations of filtering functions associated with the various subscribers in accordance with frequencies assigned to the calculations of filter stages adapted to constitute said filtering functions and the chronology of reception of said signals of subscrib

Abstract: This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory.