Abstract: A system for displaying alphanumeric and graphic information on a raster scanned display device, for example, in a teletext system, includes a memory which is updated to change the display. Dynamic changes in the displayed image are provided by assigning a base address to each of one or more zones in the memory and altering the base addresses as required under local or remote control. Alphanumeric and graphic data may be combined on a single displayed page by means of identification data associated with each row or line of data to be displayed. The required capacity of the memory associated with the display device is substantially reduced by assigning a control code to data which is to be repetitively displayed, for example, spaces at the end of a line or fields of uniform color. Selected elements are thus displayed a predetermined number of times without the need for a corresponding number of memory locations.

Abstract: Device for the testing and checking of the operation of blocks within an integrated circuit, characterized in that it is formed from a set of shift registers and logic circuits associated with each block of the circuit to be tested, the set of registers including at least one test register (35), one status register (36) and one mask register (37), the status register (36) being connected to the outputs (ST0 to ST15) of the block to be tested while the test and mask registers (35,37) and the logic circuits (38,39) are connected to a central processing unit (1) of the integrated circuit of which the blocks form part, the central processing unit (1) being also connected to the said blocks (7,10) by a common interrupt line (.SIGMA.INT).

Abstract: A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general system memory 5, or so as to constitute instructions for a video processor 2. In this latter case, the address controls an operation cycle of a first priority for controlling the processor or executes a series of operations with a lower priority, such lower priority operations allowing processor 2 to process image information without the intervention of the central unit. The invention finds application in such areas as teletext systems and video games.

Abstract: A color signal is encoded into luminance and chrominance signals. Relationships between the luminance and chrominance signals, and the color components are computed. A color component signal is generated by matrixing these relationships. In addition, a signal processor may be used to combine other video images with the color component signal.

Abstract: The point processor includes a network of memory cells (33) addressable into rows and columns (direction X and Y). A control unit (42) effects reading and writing into the network according to parameters established in advance. This processor is integrated into a video display system for various image manipulations.

Abstract: A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display p

Abstract: This device permits the distribution of the access to a RAM memory RAM (14) among a plurality of users (U1, U2, U3), the access being effected in an asynchronous manner. Certain users (U2, for example) can access the memory at adjoining addresses by means of a single row precharge cycle, the column access cycles (CAS) being successively effected during a single row (RAS) access cycle. One can thus considerably reduce the access time of the memory (14) when a large quantity of data must be read into the memory or written into it.Application to teletext terminals where the users of the memory can be the CPU, the video processor, and a teletext data receiver.

Abstract: In this apparatus, a composite memory 5 includes a managing memory (5g) containing for each line of the frame to be displayed, a word made up of information relating to the composition of the line in question. This information can define a base color, the number of memory planes, and, if appropriate, a base address of a zone of a zone memory (5z) which contains the data relating to the parts of the image which contain only typographic or graphic information. If the number of planes is equal to zero, said base color becomes a constant background color in the totality of the line to be displayed. The contents of the control memory are read out, word by word, from the control memory at the frequency of the line synchronization signal for the screen.Application to teletext systems.

Abstract: Method and apparatus for ignition control of an internal combustion engine provide for computation of an ignition instant based upon operating parameters of the engine measured during a preceding ignition cycle. A device for controlling the ignition of the engine includes a central calculating unit (17) and a peripheral input/output unit (1) controlled by a micro-code program stored in a micro-code ROM (18). Computation of engine speed is accomplished by a disk (5a) having teeth on the periphery (5b), and cooperating with a magnetic detector (5d), the disk being rigid with the crankshaft of the engine to be controlled.

Abstract: System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.