Patents by Inventor Gerard M. Salem
Gerard M. Salem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10613142Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.Type: GrantFiled: February 22, 2017Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Patent number: 10598526Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: GrantFiled: March 8, 2016Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Patent number: 10585142Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.Type: GrantFiled: September 28, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Patent number: 10571519Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.Type: GrantFiled: March 8, 2016Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mitesh A. Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem
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Patent number: 10545188Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.Type: GrantFiled: November 7, 2017Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Patent number: 10365132Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: GrantFiled: June 25, 2018Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Patent number: 10247776Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.Type: GrantFiled: February 22, 2017Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Publication number: 20190094297Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Publication number: 20190094298Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.Type: ApplicationFiled: November 7, 2017Publication date: March 28, 2019Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Patent number: 10209306Abstract: A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port.Type: GrantFiled: November 10, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Franco Motika, John D. Parker, Gerard M. Salem
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Patent number: 10203371Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.Type: GrantFiled: June 1, 2016Date of Patent: February 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Franco Motika, John D. Parker, Gerard M. Salem
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Publication number: 20180306610Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Publication number: 20180238964Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.Type: ApplicationFiled: February 22, 2017Publication date: August 23, 2018Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Publication number: 20180238962Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.Type: ApplicationFiled: February 22, 2017Publication date: August 23, 2018Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
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Publication number: 20180067162Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.Type: ApplicationFiled: November 10, 2017Publication date: March 8, 2018Inventors: Franco Motika, John D. Parker, Gerard M. Salem
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Patent number: 9857422Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.Type: GrantFiled: March 8, 2016Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Franco Motika, John D. Parker, Gerard M. Salem
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Publication number: 20170261551Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: Mitesh A. Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem
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Publication number: 20170261552Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.Type: ApplicationFiled: June 1, 2016Publication date: September 14, 2017Inventors: Franco Motika, John D. Parker, Gerard M. Salem
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Publication number: 20170261554Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: Franco Motika, John D. Parker, Gerard M. Salem
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Patent number: 9733307Abstract: A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.Type: GrantFiled: October 20, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerard M. Salem, Andrew A. Turner