Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract: A method of debugging an embedded dynamic random access memory (eDRAM) element of a processor core is provided. An aspect includes, based on an error occurring in the eDRAM element, stopping a functional clock, and not stopping a refresh clock. Another aspect includes, based on the functional clock being stopped, creating a fence signal that prevents all commands other than a refresh command, the refresh command being based on the refresh clock, from entering into the eDRAM element. Another aspect includes initializing a line fetch controller of the processor core with at least one of write data and read data. Another aspect includes restarting the functional clock. Another aspect includes performing at least one of write requests and read requests to the eDRAM element based on the at least one of the write data and the read data from the line fetch controller based on the functional clock.

Abstract: A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.

Abstract: Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

Abstract: A method of debugging a memory element is provided. The method includes initializing a line fetch controller with at least one of write data and read data; utilizing at least two separate clocks for performing at least one of write requests and read requests based on the at least one of the write data and the read data; and debugging the memory element based on the at least one of write requests and read requests.

Abstract: Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

Abstract: A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.

Abstract: A system and method of multi-frequency integrated circuit testing with a method for testing a clocked logic type integrated circuit including creating exerciser code on the integrated circuit when the integrated circuit is operating at a first frequency, switching the integrated circuit to operating at a second frequency greater than the first frequency, and running the exerciser code on the integrated circuit when the integrated circuit is operating at the second frequency.

Abstract: A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at a given address. The first set of gates provides bit outputs indicative of errors in a given memory word while the given memory word is under test. A circuit coupled to respective outputs of the first set of gates determines if a number of errors in the memory word under test exceeds the maximum number of errors correctable by the ECC.

Abstract: A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.

Abstract: A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Abstract: A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

Abstract: A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

Abstract: A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Abstract: A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at a given address. The first set of gates provides bit outputs indicative of errors in a given memory word while the given memory word is under test. A circuit coupled to respective outputs of the first set of gates determines if a number of errors in the memory word under test exceeds the maximum number of errors correctable by the ECC.

Abstract: An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.