Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

Abstract: Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results.

Abstract: Systems, methods, and processes for forming imprint lithography templates from a multi-layer substrate are described. The multi-layer substrate may include a block copolymer layer positioned on a substrate layer. The block copolymer layer may include two or more domains. At least one domain may have a different composition sensitivity than another domain such that the domains have different reactions to a specific process. Reaction of the domains to the specific process may provide a pattern in the block copolymer layer. The pattern may be transferred into the substrate layer to form the imprint lithography template.

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract: Methods for fabricating guide patterns and methods for fabricating integrated circuits using guide patterns are provided. In an embodiment, a method for fabricating a guide pattern includes forming a coating of a material with latent grafting sites and a photosensitive component configured to activate the latent grafting sites upon exposure over a substrate. The method exposes selected latent grafting sites in the coating to convert the selected latent grafting sites to active grafting sites. A grafting agent is bonded to the active grafting sites to form the guide pattern.

Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.

Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.

Abstract: Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results.

Abstract: A method includes forming a template having a plurality of elements above a process layer, wherein portions of the process layer are exposed between adjacent elements of the template. A directed self-assembly layer is formed over the exposed portions. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer. Non-periodic elements are defined in the process later by the template and periodic elements are defined in the process layer by the etch-resistant components of the directed self-assembly layer.

Abstract: Systems and methods for improving robust layer separation during the separation process of an imprint lithography process are described. Included are methods of matching strains between a substrate to be imprinted and the template, varying or modifying the forces applied to the template and/or the substrate during separation, or varying or modifying the kinetics of the separation process.

Abstract: Systems and methods for improving robust layer separation during the separation process of an imprint lithography process are described. Included are methods of matching strains between a substrate to be imprinted and the template, varying or modifying the forces applied to the template and/or the substrate during separation, or varying or modifying the kinetics of the separation process.

Abstract: Methods for forming an imprint lithography template are provided. Materials for forming the imprint lithography template may be etched at different rates based on physical properties of the layers. Additionally, reflectance of the materials may be monitored to provide substantially uniform erosion of the materials.

Abstract: Imprint lithography system may provide for an energy source for solidification of material positioned between a template and a substrate. Additionally, the energy source and/or an additional energy source may be used to clean contaminants from the template and/or the substrate.

Abstract: A silicon nanowire array including a multiplicity of silicon nanowires extending from a silicon substrate. Cross-sectional shape of the silicon nanowires and spacing between the silicon nanowires can be selected to maximize the ratio of the surface area of the silicon nanowires to the volume of the nanowire array. Methods of forming the silicon nanowire array include a nanoimprint lithography process to form a template for the silicon nanowire array and an electroless etching process to etch the template formed by the nanoimprint lithography process.

Abstract: Methods for forming an imprint lithography template are provided. Materials for forming the imprint lithography template may be etched at different rates based on physical properties of the layers. Additionally, reflectance of the materials may be monitored to provide substantially uniform erosion of the materials.

Abstract: Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE.

Abstract: Variations of interdigitated backside contact (IBC) solar cells having patterned areas formed using nano imprint lithography are described.

Abstract: Control of lateral strain and lateral strain ratio (dt/db) between template and substrate through the selection of template and/or substrate thicknesses (Tt and/or Tb), control of template and/or substrate back pressure (Pt and/or Pb), and/or selection of material stiffness are described.