Abstract: In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

Abstract: In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

Abstract: An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.

Abstract: An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output., wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.

Abstract: The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Abstract: A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Abstract: A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Abstract: A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference path includes a third data register. A learn cycle control signal is applied to a multiplexer for selecting between the data path and the reference data path and is also applied in parallel to control circuitry of a phase aligner. The learn cycle control signal is for adjusting the phase of a clock signal at a second clock output of a phase locked loop so as to optimize setup and/or hold timing at the data input of the second data register.

Abstract: A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.

Abstract: The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Abstract: The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica are matched with the flip-flop and output driver of the data paths.

Abstract: A data buffer with a mechanism to optimize the setup/hold timing at the second flip-flop (or data register) so as to reduce the propagation delay time. The data buffer has a data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, e.g. a RAM module in a memory system. The data buffer further has a clock output for providing an output clock signal to the data destination device and a phase locked loop (PLL) with a phase aligner and a first and second data register with respective clock inputs. The data input of the first data register is selectively coupled to the data input of the buffer or to a reference data input through a multiplexer. A reference data path is provided in parallel with the data path including a third data register with a data input to which the reference data input is coupled and a reference data output.

Abstract: A flip-flop has a master stage and two slave stages coupled to receive complementary outputs from the master stage. Each stage includes transfer gates and a bistable element in the form of cross-coupled inverters. The master stage bistable element switches states on a first edge of a clock signal in response to the state of a digital data input signal. The slave stage bistable elements switch states on a second dege of the clock signal in response to respective complemenary outputs from the master stage.

Abstract: A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.

Abstract: A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Abstract: An integrated CMOS circuit with a differential open drain output driver comprises a plurality of differential output stages each having differential inputs and differential outputs, the differential outputs of the differential output stages being interconnected to provide a pair of differential open drain driver outputs, and the differential inputs of the differential output stages being driven by a pair of inverter chains each of which has an input receiving one of a pair of differential input signals and cascaded inverter stages each with an output connected to an input of one of the differential output stages.

Abstract: An oscillator includes a first oscillator ring with a number of cascaded inverting delay stages and a second oscillator ring with a number of cascaded inverting delay stages. The ring oscillator also includes a number of inverter pairs which each consists of a first inverter and a second inverter, an input of the first inverter being connected with an output of the second inverter and an input of the second inverter being connected with an output of the first inverter. Each inverter pair connects a node of the first oscillator ring with a node of the second oscillator ring. Since phase noise in an oscillator is dominated by the ratio of the power in the edges of the oscillator signal versus the voltage noise that affects the delay of one oscillator stage, essentially all the consumed power is used for the switching process, implementing very steep edges of the oscillator signal.

Abstract: A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ? ? I CP2 ? t + I CP2 ? R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C?=new capacitance value=C*X C=original capacitance value.

Abstract: To generate a spread frequency spectrum clock signal in a digital approach permitting to make the key parameters independent of process, temperature and supply voltage variations, a digital phase locked loop is used. In a first step (a), a clock signal at a maximum clock frequency is generated. In a second step (b), the clock frequency is stepwise reduced by incrementally adding phase delay steps to the clock signal until a minimum clock frequency is reached. In a further step (c), the number of incrementally added phase delay steps is stepwise reduced until the maximum clock frequency is reached. Steps (a) to (c) are continuously repeated.

Abstract: A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ? ? I CP2 ? t + I CP2 ? R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C?=new capacitance value=C*X C=original capacitance value.