Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: A CMOS bus driver circuit includes an output stage of two complementary MOS transistors and an input stage, where in the connection of the source-drain paths of the MOS transistors (P1, N1) of the input stage a diode (D) is inserted so that the flow of a current in the direction of the MOS transistor (P1) connected to the supply voltage terminal (14) of the input stage is blocked, its cathode being connected to the gate of the one MOS transistor (P2) of the output stage. Connected in parallel to the diode D is the source-drain path of a further MOS transistor (P4), the gate of which is connected to the circuit output (18).

Abstract: An integrated fast bus driver circuit with reduced standby power consumption for BiCMOS processes where the power consumption of the drive circuit corresponds to the output sink current. A feedback circuit is connected to detect voltage variations at the output terminal, and vary the base current of the output bipolar transistor to oppose the voltage variations.

Abstract: The invention relates to a "power on demand" control circuit and the application thereof in a BiCMOS bus driver. The basic object resides in the creation of such a circuit with a low power need and a simple structure. This aim is to be solved by the provision of a control loop comprising a diode series circuit arrangement (D1, D2) and a bipolar transistor (Q2) between the collector and the base of the output transistor (Q1), which is of such a size that in the stable L state the base current of the outlet transistor (Q1) is so selected that the L state is maintained.