Patents by Inventor Gerhard Heier
Gerhard Heier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8242020Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.Type: GrantFiled: August 26, 2009Date of Patent: August 14, 2012Assignee: Siltronic AGInventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
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Publication number: 20100210188Abstract: The invention relates to a carrier for holding semiconductor wafers during a double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing. Some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and an inner or an outer section of a circular path.Type: ApplicationFiled: January 25, 2010Publication date: August 19, 2010Applicant: SILTRONIC AGInventors: Klaus Roettger, Gerhard Heier
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Publication number: 20100055908Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.Type: ApplicationFiled: August 26, 2009Publication date: March 4, 2010Applicant: Siltronic AGInventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
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Patent number: 7541287Abstract: A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 ?m. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.Type: GrantFiled: July 17, 2006Date of Patent: June 2, 2009Assignee: Siltronic AGInventors: Ruediger Schmolke, Thomas Buschhardt, Gerhard Heier, Guido Wenski
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Publication number: 20070021042Abstract: A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 ?m. The method provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than 115 nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.Type: ApplicationFiled: July 17, 2006Publication date: January 25, 2007Applicant: Siltronic AGInventors: Ruediger Schmolke, Thomas Buschhardt, Gerhard Heier, Guido Wenski
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Patent number: 6899762Abstract: A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmax of less than or equal to 0.13 ?m and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 ?m×1 ?m reference area. Furthermore, there is a process for producing the semiconductor wafer.Type: GrantFiled: March 28, 2003Date of Patent: May 31, 2005Assignee: Siltronic AGInventors: Guido Wenski, Wolfgang Siebert, Klaus Messmann, Gerhard Heier, Thomas Altmann, Martin Fürfanger
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Patent number: 6793837Abstract: A process is for material-removing machining, on both sides simultaneously, of semiconductor wafers having a front surface and a back surface, the semiconductor wafers resting in carriers which are set in rotation by means of an annular outer drive ring and an annular inner drive ring and being moved between two oppositely rotating working disks in a manner which can be described by means of in each case one path curve relative to the upper working disk and one path curve relative to the lower working disk, wherein the two path curves after six loops around the center have the appearance of still being open, and at each point have a radius of curvature which is at least as great as the radius of the inner drive ring.Type: GrantFiled: June 18, 2002Date of Patent: September 21, 2004Assignee: Siltronic AGInventors: Guido Wenski, Thomas Altmann, Gerhard Heier, Wolfgang Winkler, Gunther Kann
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Patent number: 6645862Abstract: A process for producing semiconductor wafers by double-sided polishing between two rotating, upper and lower polishing plates, which are covered with polishing cloth, while an alkaline polishing abrasive with colloidal solid fractions is being supplied, the semiconductor wafers being guided by carriers which have circumferential gear teeth and are set in rotation by complementary outer gear teeth and inner gear teeth of the polishing machine, which is distinguished by the following process steps: (a) at least one of the two sets of gear teeth of the polishing machine is at least from time to time sprayed with a liquid which substantially comprises water, (b) the alkaline polishing abrasive is fed continuously to the semiconductor wafers in a closed supply device. There is also a device which is suitable for carrying out the process.Type: GrantFiled: November 20, 2001Date of Patent: November 11, 2003Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AGInventors: Guido Wenski, Johann Glas, Thomas Altmann, Gerhard Heier
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Publication number: 20030186028Abstract: A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 &mgr;m×1 &mgr;m reference area. Furthermore, there is a process for producing the semiconductor wafer.Type: ApplicationFiled: March 28, 2003Publication date: October 2, 2003Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HABLEITERMATERIALIEN AGInventors: Guido Wenski, Wolfgang Siebert, Klaus Messmann, Gerhard Heier, Thomas Altmann, Martin Furfanger
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Patent number: 6583050Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.Type: GrantFiled: August 13, 2002Date of Patent: June 24, 2003Assignee: Wacker Siltronic Gesellschaft F{dot over (u)}r Halbleitermaterialien AGInventors: Guido Wenski, Thomas Altmann, Ernst Feuchtinger, Willibald Bernwinkler, Wolfgang Winkler, Gerhard Heier
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Publication number: 20030054650Abstract: A process is for material-removing machining, on both sides simultaneously, of semiconductor wafers having a front surface and a back surface, the semiconductor wafers resting in carriers which are set in rotation by means of an annular outer drive ring and an annular inner drive ring and being moved between two oppositely rotating working disks in a manner which can be described by means of in each case one path curve relative to the upper working disk and one path curve relative to the lower working disk, wherein the two path curves after six loops around the center have the appearance of still being open, and at each point have a radius of curvature which is at least as great as the radius of the inner drive ring.Type: ApplicationFiled: June 18, 2002Publication date: March 20, 2003Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Thomas Altmann, Gerhard Heier, Wolfgang Winkler, Gunther Kann
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Publication number: 20030045089Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.Type: ApplicationFiled: August 13, 2002Publication date: March 6, 2003Applicant: Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AGInventors: Guido Wenski, Thomas Altmann, Ernst Feuchtinger, Willibald Bernwinkler, Wolfgang Winkler, Gerhard Heier
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Patent number: 6514424Abstract: A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.Type: GrantFiled: April 4, 2001Date of Patent: February 4, 2003Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AGInventors: Guido Wenski, Gerhard Heier, Wolfgang Winkler, Thomas Altmann
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Patent number: 6458688Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.Type: GrantFiled: January 27, 2000Date of Patent: October 1, 2002Assignee: Wacker Siltronic Gesellschaft für Halbleiter-Materialien AGInventors: Guido Wenski, Thomas Altmann, Ernst Feuchtinger, Willibald Bernwinkler, Wolfgang Winkler, Gerhard Heier
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Publication number: 20020115387Abstract: A process for producing semiconductor wafers by double-sided polishing between two rotating, upper and lower polishing plates, which are covered with polishing cloth, while an alkaline polishing abrasive with colloidal solid fractions is being supplied, the semiconductor wafers being guided by carriers which have circumferential gear teeth and are set in rotation by complementary outer gear teeth and inner gear teeth of the polishing machine, which is distinguished by the following process steps:Type: ApplicationFiled: November 20, 2001Publication date: August 22, 2002Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Johann Glas, Thomas Altmann, Gerhard Heier
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Publication number: 20020055324Abstract: A process for the chemical-mechanical polishing of silicon wafers is by rotational movement of the silicon surface which is to be polished on a polishing plate which is covered with polishing cloth, with a continuous supply of an alkaline polishing agent which contains abrasives, at least 2 &mgr;m of material being removed from the polished silicon surface during the polishing. Immediately after the polishing has finished, and while maintaining the rotational movement, instead of the polishing agent at least two different stopping agents are supplied in succession, each removing less than 0.5 &mgr;m of material from the polished silicon surface.Type: ApplicationFiled: September 11, 2001Publication date: May 9, 2002Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Thomas Altmann, Gerhard Heier, Wolfgang Winkler
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Publication number: 20010047978Abstract: A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.Type: ApplicationFiled: April 4, 2001Publication date: December 6, 2001Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Gerhard Heier, Wolfgang Winkler, Thomas Altmann
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Publication number: 20010014570Abstract: There is a process for producing a semiconductor wafer having a front surface and a back surface and a polished edge, in which the semiconductor wafer is subjected to polishing on both sides.Type: ApplicationFiled: January 30, 2001Publication date: August 16, 2001Applicant: WACKER SILTRONIC GESELLSCHAFT FOR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Thomas Altmann, Gerhard Heier, Wolfgang Winkler