Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers

Abstract

The invention relates to a carrier for holding semiconductor wafers during a double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing. Some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and an inner or an outer section of a circular path.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to German application DE 10 2009 009 497.0 filed Feb. 18, 2009, which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers. The invention also relates to a method for the double-side polishing of semiconductor wafers in which the carrier is used.

2. Background Art

The production of semiconductor wafers for use as substrates for producing electronic components regularly comprises at least one double-side polishing of the semiconductor wafers, which is carried out in one step and hereinafter is called DSP. During DSP, a semiconductor wafer is situated together with further semiconductor wafers between upper and lower rotating polishing plates that are covered with polishing cloth. Carriers, having cutouts in which the semiconductor wafers lie, guide and hold the semiconductor wafers during polishing. The carriers have on their periphery, an outer toothing by means of which they are rotated as planetary gears of a planetary gear mechanism about their own axis and the axis of the polishing plates during polishing. The semiconductor wafers are polished in the presence of polishing agent that is supplied from the upper polishing plate and is distributed on the polishing cloths. It is necessary to ensure that both sides of the semiconductor wafer are sufficiently supplied with polishing agent in order that a uniform polishing material removal is obtained. The sufficient supply of polishing agent is particularly important if polishing is effected by means of a polishing machine of compact design. This type of machine accommodates only one carrier, which extends over the entire lower polishing plate, and the polishing plates and the carrier have a common axis of rotation. In this case, a lack of polishing agent has the effect that the semiconductor wafer is restricted in its mobility with regard to the rotation about its own axis to an extent such that accumulated frictional heat brings about increased material removal in a partial region of the edge of the semiconductor wafer and a semiconductor wafer having a wedge-shaped edge section thus arises. In order to prevent this, EP 1 676 672 A1 proposes improving the supply of polishing agent to the lower polishing plate by at least 15% of the area of the carrier being occupied by holes that provide the polishing agent with a passage to the lower polishing plate.

The inventors of the present invention have determined, however, that a quantitively sufficient supply of polishing agent to the lower polishing plate is admittedly necessary, but does not necessarily counteract all faults of the edge geometry. This applies in particular to the so-called edge roll-off, which concerns the entire wafer edge and is observed after DSP. The edge roll-off is described in SEMI standard M69 as a surface deviation in the edge region of semiconductor wafers having a large diameter. Since more and more area of a semiconductor wafer is being qualified for the production of electronic components and the edge exclusion in present-day extremely high quality semiconductor wafers is only 1 mm, there is a growing interest in reducing geometry faults in the edge region. Standardized parameters, for example the ESFQR defined in the SEMI standard, are available for quantitively describing such geometry faults.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide means with the aid of which the edge roll-off after DSP can be significantly reduced, and a semiconductor wafer having an advantageous edge geometry becomes available. These and other objects are achieved by means of a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during polishing, wherein some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged on a path which lies at a distance of 1 to 10 mm concentrically around the cutouts and has an inner section, an outer section and two sections between the inner and outer sections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a carrier representing the prior art.

FIG. 2 shows a carrier according to the invention in a first embodiment.

FIG. 3 shows a carrier according to the invention in a second embodiment.

FIG. 4 shows a carrier according to the invention in a third embodiment.

FIGS. 5 and 6 show the different effect which a carrier according to the invention has on the edge geometry of a semiconductor wafer after a DSP in comparison with a carrier associated with the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The inventors have discovered that access for the polishing agent to the lower polishing plate, which is situated near to the wafer edge and is arranged at a uniform distance at the wafer edge, makes a significant contribution to reducing edge roll-off. Therefore, the carrier according to the invention has not only the customary passage openings for polishing agent, but also those which are positioned in accordance with this insight. It can be used together with others in a polishing machine with a planetary gear mechanism or by itself in a polishing machine of compact design.

The carrier is composed preferably of steel, plastic or ceramic, most preferably of hardened steel and is provided, if appropriate, with a low-abrasion and low-friction coating.

The cutouts for receiving semiconductor wafers are lined with plastic in the customary manner in order to protect the sensitive wafer edge, preferably with inlays having cutouts at regular distances of 5 to 30 mm. A particularly preferred form of inlays is described for example in DE 100 18 338 C1.

The passage openings for polishing agent which are arranged away from the cutouts can in principle be shaped as desired. Openings having a periphery in the shape of rounded triangles and quadrangles or of circles are preferred. Passage openings such as are described in DE 102 47 200 A1 are particularly preferred.

The invention is explained in more detail below with reference to figures.

The carrier in accordance with FIG. 1, which represents the prior art, comprises cutouts 1 for receiving semiconductor wafers and relatively large passage openings 2 for a polishing agent supplied during the polishing.

The carrier embodied according to the invention in accordance with FIG. 2 differs from that shown in FIG. 1 essentially by virtue of a ring of smaller passage openings composed of holes 3. The holes have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the distance denotes the shortest distance between the hole edge and the edge of the cutout without taking account of an inlay. The midpoints of the holes lie on a concentric circular path around the cutouts. In accordance with the first embodiment of the carrier, this circular path is completely occupied by the holes. Further embodiments provide for the holes to form a ring that is open in one section. If the circular path is regarded as subdivided into four sections having an approximately identical length, it is possible to differentiate between holes 3a arranged on an inner section, holes 3b arranged on an outer section, and holes 3c and 3d arranged on two central sections lying between the inner and outer sections.

In the case of the carrier in accordance with the second embodiment, which is illustrated in FIG. 3, the holes are not arranged around the entire circumference of the circular path. This is because the inventors have discovered that occupying the central sections with holes already suffices to obtain a significantly smaller edge roll-off, particularly if the carrier is used as a planetary gear. The additional arrangement of holes on the inner and/or the outer section primarily increases the stiffness of the carrier. Accordingly, the holes in the case of the carrier in accordance with the second embodiment are arranged on the central sections and additionally on the outer section.

In the case of the carrier in accordance with the third embodiment, which is illustrated in FIG. 4, holes are arranged on the two central sections and on the inner section of the circular path.

The distance between adjacent holes of a section is 3 to 30 mm and is preferably always the same, including between two adjacent holes of adjacent sections.

EXAMPLE

Semiconductor wafers composed of silicon having a diameter of 300 mm were polished on a DSP machine of the AC2000 type from the manufacturer Peter

Wolters under the same conditions, and the edge roll-off was examined. Carriers in accordance with a first embodiment of the invention were used in one experiment, and carriers embodied in accordance with the illustration in FIG. 1 were used in a comparative experiment.

FIG. 5 and FIG. 6 show the surface contour of the front side of two of the polished semiconductor wafers, plotted as distance A along the diameter D.

In the case of the semiconductor wafer polished according to the invention, the surface contour of which wafer is illustrated in FIG. 5, virtually no edge roll-off is discernable. By contrast, a semiconductor wafer polished in accordance with the comparative experiment, the surface contour of the wafer being illustrated in FIG. 6, exhibits a pronounced edge roll-off The ESFQR, measured taking account of an edge exclusion of 1 mm, was particularly low in the case of semiconductor wafers polished according to the invention. Measurements on a multiplicity of semiconductor wafers polished according to the invention showed that the ESFQR_max, that is to say the ESFQR in the sectors having the worst edge geometry, varied within the range of 100 to 170 nm.

While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.

Claims

1. A carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing, wherein some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and on at least one of an inner or an outer section of a circular path.

2. The carrier of claim 1, wherein the holes have an identical distance between holes of 3 to 30 mm.

3. The carrier of claim 1, wherein the holes are arranged on the central sections and additionally on the outer section and the inner section of the circular path.

4. The carrier of claim 2, wherein the holes are arranged on the central sections and additionally on the outer section and the inner section of the circular path.

5. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 1, during double-side polishing.

6. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 2, during double-side polishing.

7. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 3, during double-side polishing.

8. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 4, during double-side polishing.