Patents by Inventor Gerhard Koops
Gerhard Koops has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10171007Abstract: A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.Type: GrantFiled: December 19, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Publication number: 20180109203Abstract: A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.Type: ApplicationFiled: December 19, 2017Publication date: April 19, 2018Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 9859818Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.Type: GrantFiled: December 8, 2014Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 9142625Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.Type: GrantFiled: October 12, 2012Date of Patent: September 22, 2015Assignee: NXP B.V.Inventors: Anco Heringa, Gerhard Koops, Boni Kofi Boksteen, Alessandro Ferrara
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Patent number: 9017561Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.Type: GrantFiled: August 28, 2013Date of Patent: April 28, 2015Assignee: NXP, B.V.Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
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Publication number: 20150091411Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 8980698Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element 14. A sacrificial layer 20 is provided over the device element and a package cover layer 24 is provided over the sacrificial layer. A spacer layer 13 is formed over the sacrificial layer and is etched to define spacer portions adjacent an outer side wall of the sacrificial layer. These improve the hermetic sealing of the side walls of the cover layer 24.Type: GrantFiled: November 10, 2009Date of Patent: March 17, 2015Assignee: NXP, B.V.Inventors: Greja Johanna Adriana Verheijden, Gerhard Koops
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Patent number: 8906729Abstract: The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.Type: GrantFiled: November 9, 2012Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 8818265Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.Type: GrantFiled: April 24, 2012Date of Patent: August 26, 2014Assignee: NXP B.V.Inventors: Peter Gerard Steeneken, Maarten Jacobus Swanenberg, Henk Boezen, Gerhard Koops, Frans Bontekoe, Reinout Woltjer
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Publication number: 20140145297Abstract: An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: NXP B.V.Inventors: Roel DAAMEN, Gerhard KOOPS, Peter Gerard STEENEKEN
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Publication number: 20140103968Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: NXP B.V.Inventors: ANCO HERINGA, GERHARD KOOPS, BONI KOFI BOKSTEEN, ALESSANDRO FERRARA
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Publication number: 20140001147Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.Type: ApplicationFiled: August 28, 2013Publication date: January 2, 2014Applicant: NXP B. V.Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
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Patent number: 8592228Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).Type: GrantFiled: November 15, 2007Date of Patent: November 26, 2013Assignee: NXP, B.V.Inventors: Johannes Donkers, Erwin Hijzen, Philippe Meunier-Beillard, Gerhard Koops
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Patent number: 8569934Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.Type: GrantFiled: December 23, 2010Date of Patent: October 29, 2013Assignee: NXP B.V.Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
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Publication number: 20130281033Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Inventors: Peter Gerard Steeneken, Maarten Jacobus Swanenberg, Henk Boezen, Gerhard Koops, Frans Bontekoe, Reinout Woltjer
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Patent number: 8426928Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.Type: GrantFiled: October 29, 2010Date of Patent: April 23, 2013Assignee: NXP B.V.Inventors: Johannes van Wingerden, Greja Johanna Adriana Maria Verheijden, Gerhard Koops, Jozef Thomas Martinus van Beek
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Patent number: 8330238Abstract: A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.Type: GrantFiled: November 23, 2010Date of Patent: December 11, 2012Assignee: NXP B.V.Inventors: Johannes van Wingerden, Wim van den Einden, Harold H. Roosen, Greja Johanna Adriana Maria Verheijden, Gerhard Koops, Didem Ernur, Jozef Thomas Martinus van Beek
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Patent number: 8310053Abstract: A micro-device with a cavity, the micro-device including a substrate. A method of forming the micro-device includes the steps of: A) providing the substrate having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant; and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity , i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.Type: GrantFiled: April 22, 2009Date of Patent: November 13, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 8273653Abstract: A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.Type: GrantFiled: June 3, 2009Date of Patent: September 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
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Patent number: 8260098Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.Type: GrantFiled: February 17, 2011Date of Patent: September 4, 2012Assignee: NXP B.V.Inventors: Dusan Golubovic, Gerhard Koops, Tony Vanhoucke, Rob Van Dalen