Patents by Inventor Gerhard Koops

Gerhard Koops has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120213466
    Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 23, 2012
    Inventors: Dusan Golubovic, Gerhard Koops, Tony Vanhoucke, Rob Van Dalen
  • Patent number: 8143971
    Abstract: A MEMS resonator, comprising a planar resonator body formed of two different materials with opposite sign temperature coefficient of Young's modulus. A first portion of one material extends across the full thickness of the resonator body. This provides a design which allows reduced temperature drift.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jozef Thomas Beek, Johannes van Wingerden, Wim van den Einden, Kim Phan Le, Gerhard Koops, Cas van der Avoort
  • Publication number: 20110210435
    Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element 14. A sacrificial layer 20 is provided over the device element and a package cover layer 24 is provided over the sacrificial layer. A spacer layer 13 is formed over the sacrificial layer and is etched to define spacer portions adjacent an outer side wall of the sacrificial layer. These improve the hermetic sealing of the side walls of the cover layer 24.
    Type: Application
    Filed: November 10, 2009
    Publication date: September 1, 2011
    Applicant: NXP B.V.
    Inventors: Greja Johanna Adriana Verheijden, Gerhard Koops
  • Publication number: 20110186941
    Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.
    Type: Application
    Filed: October 29, 2010
    Publication date: August 4, 2011
    Applicant: NXP B.V.
    Inventors: Johannes van WINGERDEN, Greja Johanna Adriana Maria VERHEIJDEN, Gerhard KOOPS, Jozef Thomas Martinus van BEEK
  • Publication number: 20110181153
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Application
    Filed: December 23, 2010
    Publication date: July 28, 2011
    Applicant: NXP B.V.
    Inventors: Gerhard KOOPS, Jozef Thomas Martinus van BEEK
  • Publication number: 20110175178
    Abstract: A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.
    Type: Application
    Filed: November 23, 2010
    Publication date: July 21, 2011
    Applicant: NXP B.V.
    Inventors: Johannes van WINGERDEN, Wim van den EINDEN, Harold H. ROOSEN, Greja Johanna Adriana Maria VERHEIJDEN, Gerhard KOOPS, Didem ERNUR, Jozef Thomas Martinus van BEEK
  • Publication number: 20100244125
    Abstract: A power semiconductor device comprises a conductive gate, provided in an upper part of a trench (11) formed in a semiconductor substrate (1), and a conductive field plate, extending in the trench, parallel to the conductive gate, to a depth greater that the conductive gate. The field plate is insulated from the walls and bottom of the trench by a field plate insulating layer that is thicker than the gate insulating layer. In one embodiment, the field plate is insulated within the trench from the gate. Impurity doped regions of a first conductivity type are provided at the surface of the substrate adjacent the first and second sides of the trench and form source and drain regions, and a body region (7) of second conductivity type is formed under the source region on the first side of the trench (11). The conductive gate is insulated from the body region (7) by a gate insulating layer. A method of making the semiconductor device is compatible with conventional CMOS processes.
    Type: Application
    Filed: March 26, 2007
    Publication date: September 30, 2010
    Applicant: NXP B.V.
    Inventors: Jan Sonsky, Gerhard Koops, Rob Van Dalen
  • Publication number: 20100052081
    Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).
    Type: Application
    Filed: November 15, 2007
    Publication date: March 4, 2010
    Applicant: NXP, B.V.
    Inventors: Johannes Donkers, Erwin Hijzen, Philippe Meunier-Beillard, Gerhard Koops
  • Publication number: 20100026421
    Abstract: A MEMS resonator, comprising a planar resonator body formed of two different materials with opposite sign temperature coefficient of Young's modulus. A first portion of one material extends across the full thickness of the resonator body. This provides a design which allows reduced temperature drift.
    Type: Application
    Filed: July 10, 2009
    Publication date: February 4, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jozef Thomas BEEK, Johannes Van WINGERDEN, Wim Van den EINDEN, Kim Phan LE, Gerhard KOOPS, Cas Van der AVOORT
  • Publication number: 20100006957
    Abstract: A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.
    Type: Application
    Filed: June 3, 2009
    Publication date: January 14, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria VERHEIJDEN, Roel Daamen, Gerhard Koops
  • Publication number: 20090267166
    Abstract: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide region (20, 107, 115) with a porous layer (40, 114, 124) being permeable to a vapor HF etchant (100), and C) selectively etching the sacrificial oxide region (20, 107, 115) through the porous layer (40, 114, 124) using the vapor HF etchant (100) to obtain the cavity (50). This method may be used in the manufacture of various micro-devices with a cavity (50), i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 29, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops