Abstract: In accordance with an embodiment, microelectromechanical microphone includes a holder and a sound detection unit carried on the holder. The sound detection unit includes a planar first membrane, a planar second membrane arranged at a distance from the first membrane, a low-pressure chamber formed between the first membrane and the second membrane, a reduced gas pressure relative to normal pressure being present in the low-pressure chamber, a reference electrode arranged at least in sections in the low-pressure chamber, where the first and second membranes are displaceable relative to the reference electrode by sound waves to be detected, the reference electrode includes a planar base section and a stiffening structure provided on the base section, and the stiffening structure is provided on a side of the base section that faces the first membrane or/and on a side of the base section that faces the second membrane.

Abstract: In accordance with an embodiment, a MEMS device includes a first membrane element, a second membrane element spaced apart from the first membrane element, a low pressure region between the first and second membrane elements, the low pressure region having a pressure less than an ambient pressure, and a counter electrode structure comprising a conductive layer, which is at least partially arranged in the low pressure region or extends in the low pressure region. The conductive layer includes a segmentation providing an electrical isolation between a first portion of the conductive layer and a second portion of the conductive layer.

Abstract: A microelectromechanical microphone includes a reference electrode, a first membrane arranged on a first side of the reference electrode and displaceable by sound to be detected, and a second membrane arranged on a second side of the reference electrode, said second side being situated opposite the first side of the reference electrode, and displaceable by sound to be detected. A region of one from the first and second membranes that is displaceable by sound relative to the reference electrode, independently of said region's position relative to the reference electrode, can comprise a planar section and also an undulatory section adjoining the planar section and arranged in a region of overlap one of the first membrane or the second membrane with the other one of the first membrane and or the second membrane.

Abstract: In accordance with an embodiment, a MEMS device includes a first membrane element, a second membrane element spaced apart from the first membrane element, a low pressure region between the first and second membrane elements, the low pressure region having a pressure less than an ambient pressure, and a counter electrode structure comprising a conductive layer, which is at least partially arranged in the low pressure region or extends in the low pressure region. The conductive layer includes a segmentation providing an electrical isolation between a first portion of the conductive layer and a second portion of the conductive layer.

Abstract: A method for manufacturing a semiconductor device includes providing a carrier wafer; and forming a semiconductor device layer on the carrier wafer. After front side processing of the semiconductor device layer, the carrier wafer is removed by cutting along a plane which is parallel to the semiconductor device layer.

Abstract: In accordance with an embodiment, a MEMS device includes a first membrane element, a second membrane element spaced apart from the first membrane element, a low pressure region between the first and second membrane elements, the low pressure region having a pressure less than an ambient pressure, and a counter electrode structure comprising a conductive layer, which is at least partially arranged in the low pressure region or extends in the low pressure region. The conductive layer includes a segmentation providing an electrical isolation between a first portion of the conductive layer and a second portion of the conductive layer.

Abstract: In accordance with an embodiment, a MEMS device includes a first membrane element, a second membrane element spaced apart from the first membrane element, a low pressure region between the first and second membrane elements, the low pressure region having a pressure less than an ambient pressure, and a counter electrode structure comprising a conductive layer, which is at least partially arranged in the low pressure region or extends in the low pressure region. The conductive layer includes a segmentation providing an electrical isolation between a first portion of the conductive layer and a second portion of the conductive layer.

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.