Patents by Inventor Gerhard Noebauer
Gerhard Noebauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072785Abstract: An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.Type: ApplicationFiled: August 9, 2023Publication date: February 29, 2024Inventors: Adrian Finney, Oliver Blank, Gerhard Prechtl, Dirk Ahlers, Gerhard Nöbauer, Marius Aurel Bodea, Joachim Schönle, Oliver Häberlen
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Patent number: 11901355Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.Type: GrantFiled: December 21, 2022Date of Patent: February 13, 2024Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Florian Gasser
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Publication number: 20240047431Abstract: A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: Angela Kessler, Josef Hoeglauer, Gerhard Noebauer
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Patent number: 11876041Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.Type: GrantFiled: December 20, 2021Date of Patent: January 16, 2024Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Gerhard Noebauer
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Patent number: 11817430Abstract: A semiconductor module includes a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Both transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.Type: GrantFiled: September 21, 2021Date of Patent: November 14, 2023Assignee: Infineon Technologies Austria AGInventors: Angela Kessler, Josef Hoeglauer, Gerhard Noebauer
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Publication number: 20230253304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20230208301Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.Type: ApplicationFiled: December 19, 2022Publication date: June 29, 2023Inventor: Gerhard Nöbauer
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Patent number: 11664304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20230143329Abstract: A transistor arrangement includes a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor, and wherein a resistance of the second source conductor is different from a resistance of the first source conductor.Type: ApplicationFiled: January 4, 2023Publication date: May 11, 2023Inventor: Gerhard Noebauer
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Publication number: 20230120226Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.Type: ApplicationFiled: December 21, 2022Publication date: April 20, 2023Inventors: Gerhard Noebauer, Florian Gasser
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Patent number: 11581369Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.Type: GrantFiled: December 10, 2020Date of Patent: February 14, 2023Assignee: Infineon Technologies Austria AGInventors: Sylvain Leomant, Gerhard Noebauer, Thomas Oszinda, Christian Gruber, Sergey Ananiev
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Patent number: 11575041Abstract: A method of current detection includes providing a transistor arrangement which comprises a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each having a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each having a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor; and detecting a first current flowing between the drain node and the first source node of the transistor arrangement, wherein detecting the first current includes measuring a second current flowing between the drain node and the second source node of the transistor arrangement.Type: GrantFiled: November 25, 2020Date of Patent: February 7, 2023Assignee: Infineon Technologies Austria AGInventor: Gerhard Noebauer
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Patent number: 11574904Abstract: In an embodiment, a semiconductor device is provided that includes a main transistor having a load path, a sense transistor configured to sense a main current flowing in the load path of the main transistor, and at least one bypass diode structure configured to protect the sense transistor. The at least one bypass diode structure is electrically coupled in parallel with the sense transistor.Type: GrantFiled: May 5, 2020Date of Patent: February 7, 2023Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Florian Gasser
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Publication number: 20220254703Abstract: In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.Type: ApplicationFiled: April 29, 2020Publication date: August 11, 2022Inventors: Elvir Kahrimanovic, Gerhard Noebauer, Oliver Blank, Alessandro Ferrara
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Publication number: 20220115314Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Oliver Blank, Gerhard Noebauer
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Publication number: 20220108945Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: ApplicationFiled: October 5, 2021Publication date: April 7, 2022Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20220093573Abstract: A semiconductor module includes a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Both transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.Type: ApplicationFiled: September 21, 2021Publication date: March 24, 2022Inventors: Angela Kessler, Josef Hoeglauer, Gerhard Noebauer
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Publication number: 20220084915Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.Type: ApplicationFiled: September 10, 2021Publication date: March 17, 2022Inventors: Sergey Yuferev, Josef Hoeglauer, Gerhard Noebauer, Hao Zhuang
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Patent number: 11239147Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.Type: GrantFiled: July 2, 2020Date of Patent: February 1, 2022Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Gerhard Noebauer
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Publication number: 20210351168Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.Type: ApplicationFiled: May 4, 2021Publication date: November 11, 2021Inventors: Gerhard Noebauer, Sergey Yuferev