Patents by Inventor Gerhard Noebauer
Gerhard Noebauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190035915Abstract: Disclosed is a transistor device. The transistor device includes: in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region; a gate electrode dielectrically insulated from the body region by a gate dielectric; a source electrode electrically connected to the source region; at least one field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a rectifier element coupled between the source electrode and the field electrode. The field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body. The rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region.Type: ApplicationFiled: July 25, 2018Publication date: January 31, 2019Inventors: Ralf Siemieniec, Robert Haase, Gerhard Noebauer, Martin Poelzl
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Publication number: 20190006357Abstract: A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.Type: ApplicationFiled: June 27, 2018Publication date: January 3, 2019Inventors: Cedric Ouvrard, Cesar Augusto Braz, Olivier Guillemant, David Laforet, Gerhard Noebauer, Li Juin Yip
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Patent number: 10068848Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.Type: GrantFiled: January 12, 2017Date of Patent: September 4, 2018Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
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Patent number: 9978862Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.Type: GrantFiled: April 30, 2013Date of Patent: May 22, 2018Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Publication number: 20180047719Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.Type: ApplicationFiled: September 19, 2017Publication date: February 15, 2018Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Patent number: 9799643Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.Type: GrantFiled: May 23, 2013Date of Patent: October 24, 2017Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Walter Rieger, Martin PöIzl, Gerhard Nöbauer
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Publication number: 20170288654Abstract: A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.Type: ApplicationFiled: April 3, 2017Publication date: October 5, 2017Inventors: Ralf Otremba, Josef Hoeglauer, Gerhard Noebauer
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Publication number: 20170125345Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
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Patent number: 9570553Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.Type: GrantFiled: August 19, 2013Date of Patent: February 14, 2017Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
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Patent number: 9537400Abstract: A device and method for operating a switching power converter are disclosed. In an embodiment a circuit includes a switching power converter having a half bridge including a high-side semiconductor switch connected to a low-side semiconductor switch and an inductor coupled to a half-bridge output node. The circuit further includes a control circuit configured to generate drive signals to switch the high-side semiconductor switch and the low-side semiconductor switch on and off, wherein the drive signals are generated to ensure a dead time between a switch-off of the low-side switch and a subsequent switch-on of the high side switch, and wherein the dead time is set to a first value, when an inductor current is negative at a time of switching, and the dead time is set to a second value, which is lower than the first value, when the inductor current is positive at the time of switching.Type: GrantFiled: August 29, 2014Date of Patent: January 3, 2017Assignee: Infineon Technologies Austria AGInventor: Gerhard Noebauer
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Patent number: 9431392Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.Type: GrantFiled: March 15, 2013Date of Patent: August 30, 2016Assignee: Infineon Technologies Austria AGInventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
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Publication number: 20160112041Abstract: A power transistor model is described which comprises a source drain path, a first current source and a voltage controlled second current source in the source drain path which model the static voltage-current-relationship of a modeled power transistor, wherein the voltage-controlled second current source models a nonlinear behavior of a drift zone of the power transistor.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventors: Kevni Bueyuektas, Uwe Wahl, Andreas Schloegl, Gerhard Noebauer
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Publication number: 20160065065Abstract: A device and method for operating a switching power converter are disclosed. In an embodiment a circuit includes a switching power converter having a half bridge including a high-side semiconductor switch connected to a low-side semiconductor switch and an inductor coupled to a half-bridge output node. The circuit further includes a control circuit configured to generate drive signals to switch the high-side semiconductor switch and the low-side semiconductor switch on and off, wherein the drive signals are generated to ensure a dead time between a switch-off of the low-side switch and a subsequent switch-on of the high side switch, and wherein the dead time is set to a first value, when an inductor current is negative at a time of switching, and the dead time is set to a second value, which is lower than the first value, when the inductor current is positive at the time of switching.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventor: Gerhard Noebauer
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Publication number: 20150380348Abstract: A semiconductor package includes a semiconductor chip having a semiconductor body having a main surface and a rear surface opposite the main surface. Control terminals and output terminals are arranged on the main surface. A first metallization layer is formed along the rear surface. A bidirectional switching device is integrated in the semiconductor body and is configured to conduct or block current flowing between the first and second output terminals, based on a biasing of the control terminals. The first metallization layer electrically connects an internal node of the bidirectional switching device. The package further includes a chip-carrier comprising leads extending away from a chip mounting surface. The semiconductor chip is affixed and the main surface with the control terminals and output terminals connected to the lead frame. The package further includes an electrically insulating structure encapsulating the semiconductor chip and exposing the leads.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Gerhard Noebauer, Josef Hoeglauer
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Patent number: 9123701Abstract: A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed.Type: GrantFiled: July 11, 2013Date of Patent: September 1, 2015Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Josef Höglauer, Gerhard Nöbauer, Martin Pölzi
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Patent number: 9105470Abstract: A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.Type: GrantFiled: April 10, 2014Date of Patent: August 11, 2015Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
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Publication number: 20150048445Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl
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Publication number: 20150014858Abstract: A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed.Type: ApplicationFiled: July 11, 2013Publication date: January 15, 2015Inventors: Ralf Otremba, Josef Höglauer, Gerhard Nöbauer, Martin Pölzl
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Patent number: 8907418Abstract: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.Type: GrantFiled: May 7, 2013Date of Patent: December 9, 2014Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
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Publication number: 20140346569Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer