Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format;—a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (?V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (?V2) equal to ½L of the product of the first voltage step (?V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (?V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (?V2) equal to ½ L of the product of the first voltage step (?V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: A boosted sampling circuit that is relatively straightforward to form is provided, as well as a corresponding method for driving the same. The input voltage applied to the boosted sampling circuit may be equal to a supply voltage or may be greater than a maximum voltage level allowed by the prior art circuits. This result is attained by connecting the control nodes of a plurality of switches to the input node while a first control phase is active, and by connecting a current terminal of another switch to a biasing voltage for protecting it from breakdowns.

Abstract: The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp?Vrefm)/2]*(C4?C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract: A boosted sampling circuit that is relatively straightforward to form is provided, as well as a corresponding method for driving the same. The input voltage applied to the boosted sampling circuit may be equal to a supply voltage or may be greater than a maximum voltage level allowed by the prior art circuits. This result is attained by connecting the control nodes of a plurality of switches to the input node while a first control phase is active, and by connecting a current terminal of another switch to a biasing voltage for protecting it from breakdowns.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (&Dgr;V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (&Dgr;V2) equal to ½L of the product of the first voltage step (&Dgr;V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: The circuit comprises a differential amplifier (10) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C1p) and a second (1m) capacitor and first (C3) and second (C4) capacitive means that by means of controlled switches (SW9-SW12) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C1p) and the second (C1m) capacitor or between a first (VB) and a second (Vref1) reference voltage terminal.

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract: A processing unit with balanced outputs transfers a received digital signal to an amplification unit with balanced inputs and outputs. A control unit enables or disables the processing and amplification units in response to a power up/power down signal. To prevent disturbances due to power up/power down transients from appearing in a speaker connected between the outputs of the amplification unit, switches are provided between the outputs of the processing unit and the inputs of the amplification unit. A delay circuit generates according to a predetermined timing program enabling/disabling control signals for the processing and amplification units, and generates control signals for the switches.

Abstract: A telephone receiving section having a final stage, an electroacoustic transducer having a first terminal connected to the ground of the circuit, a unit for controlling switching on/off, a source of a reference voltage, a switch that can adopt a first position or a second position in order to connect the second terminal of the transducer selectively, via a capacitor, to a reference-voltage terminal of the reference voltage source or to an output terminal of the final stage, respectively, and control means that respond to signals of the unit for controlling switching on/off in order to activate or to deactivate the final stage and the reference-voltage source and to operate the switch in accordance with a predetermined time program. The receiving section operates with the same immunity to disturbances as a fully balanced structure, even though the transducer is not connected between two balanced outputs.

Abstract: A processing unit with balanced outputs transfers a received digital signal to an amplification unit with balanced inputs and outputs. A control unit enables or disables the processing and amplification units in response to a power up/power down signal. To prevent disturbances due to power up/power down transients from appearing in a speaker connected between the outputs of the amplification unit, switches are provided between the outputs of the processing unit and the inputs of the amplification unit. A delay circuit generates according to a predetermined timing program enabling/disabling control signals for the processing and amplification units, and generates control signals for the switches.

Abstract: The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Abstract: A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.

Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.

Abstract: A receiver portion of a telephone includes a differential amplifier stage with a single output, an electroacoustic transducer connected between the output, via a capacitor and ground and a unit for controlling switching on/off, connected to the differential stage for the activation or deactivation thereof. To prevent annoying noises in the transducer upon switching on and off, the differential stage includes an operational amplifier having a first capacitor and a second capacitor in series with the inverting and the non-inverting input terminals. A third capacitor is connected between the inverting input and the output of the operational amplifier. A fourth capacitor is connected between the non-inverting input and a first reference-voltage terminal. A first switching capacitor is alternatively connectable between a second and a third reference-voltage terminal, or between the first input and the output of the operational amplifier.

Abstract: An area-efficient reconstruction filter removes undesirable sample images produced by current-driven digital-to-analog converters. The reconstruction filter includes: an input node for receiving the input current signal; an operational amplifier having first and second inputs and an output at which the output voltage signal is produced; a first resistor coupled between the output of the operational amplifier and the input node; a second resistor coupled to the first input of the operational amplifier; and a third resistor coupled between the input node and the second resistor. The reconstruction filter may also include a fourth resistor coupled between the input node and a reference voltage.

Abstract: The boosted switch device comprises an input terminal and an output terminal; a supply line set to a supply potential; a ground line set to a ground potential; a transistor connected between the input and output terminals; a capacitor; and a switch device connecting the capacitor between the supply line and the ground line, when the transistor is off, and between the input terminal and the control terminal of the transistor, when the transistor is on.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.