Abstract: A circuit arrangement for enhancing the transconductance of a differential amplifier stage comprising a pair of MOS transistors, having respective source electrodes connected together through a circuit node, comprises a pair of active components respectively connected in each of the connections between the aforesaid electrodes and the aforesaid node and serving a characteristic function corresponding to that of a negative value resistor. This arrangement enables the transconductance of the differential stage to be increased while keeping the dissipated electric power low and the area occupied in an integrated circuit small.

Abstract: The preamplifier includes a first amplifier stage (M1A, M2A) and a second amplifier stage (M1, M2), both of which are of the differential type, have the same dimensions, have their output nodes connected in parallel to one another, and drive a load formed by a current mirror (M3, M4). A third differential amplifier stage with single-ended output (M6, M7, M8, M9, M10, M11) driven by the current mirror supplies the final output voltage of the preamplifier. The input nodes of the first stage act as input for the differential signal to be amplified, and the input nodes of the second stage are driven respectively by a preset reference voltage (V.sub.CM) and by a voltage (V.sub.x) which is proportional to the final output voltage of the preamplifier.

Abstract: The filter comprises at least one completely differential operational amplifier having two inputs and two outputs and at least one pair of feedback circuits connecting said outputs with respective inputs of said amplifier outside of same. The operational amplifier has no common-mode feedback circuit, whose functions are performed by said feedback circuits external to the amplifier.

Abstract: An all-differential operational amplifier (20) has a first input (22) and a second input (24) and correspondingly has a first output (26) and a second output (28), fed back on its own input respectively through a first (34) and second (36) impedance which are generally resistive and have identical values. The first output is connected to the second input of the operational amplifier across a third impedance (32). A fourth impedance (30), equal in value to the third impedance, is connected in series to the first input and acts as input terminal of the converter. The resistive components of the impedance can be implemented as switched capacitors.

Abstract: A circuit arrangement for increasing the gain-bandwidth product of a CMOS amplifier having a differential cell input stage comprises, within said input stage:a pair of active components having a characteristic function which corresponds with that of a negative value resistor, for increasing the transconductance of the stage,a pair of capacitors being each respectively associated with a corresponding one of the active components to introduce a pole/zero pair in the frequency response from the amplifier, andan additional input stage cross-connected to the differential cell for bringing the frequency value of the zero a predetermined distance away from the amplifier clipping frequency.

Abstract: A method of reconstructing an analog signal, particularly for digital telephony, comprises a first step of digital-to-analog conversion, wherein a first reconstruction of the analog signal is provided by introducing a distortion component into the frequency spectrum whose amplitude decreases with the signal frequency, and a second step of filtering carried out by means of a reconstruction filter provided with integrators and having a cut-off frequency F.sub.t. That attenuating distortion component is utilized instead of one of the integrators in the reconstruction filter, to afford a reduction of the overall design of the circuit device operating in accordance with this method, and bring about, as a result, decreased occupation of the integrated circuit and power dissipation.

Abstract: A high resolution, fully differential, CMOS comparator advantageously employs a single high-gain, "folded cascode", fully differential operational amplifier and an output latch circuit and the output common mode control of the high-gain amplifier is implemented without requiring the use of a conventional control circuit, thus improving layout economy. The common mode control is performed by providing the latch with a differential input stage through which a common mode feedback network is realized which acts upon a pair of output transistors of the operational amplifier for effectively controlling the output common mode thereof. The comparator has a simplified layout and is remarkably faster because it has no additional capacitances loading the outputs of the amplifier.

Abstract: The sampled-data band-pass filter device is based on the phenomemon of aliasing, and allows the substantially unattenuated passage of the components of an input signal at a frequency included within an interval comprised between a first frequency (f.sub.sL) and a second frequency (f.sub.sH), arranged around a third frequency (f.sub.sO), while it substantially attenuates the components of the input signal at frequencies outside said interval, and furthermore automatically performs the shift to low-frequency, around a fourth frequency (f.sub.O), of the components of the input signal which have passed without attenuation. According to the invention, the device comprises, as filter element, a sampled-data band-pass filter which employs, as sampling frequency, a fifth frequency (f.sub.s) equal to a whole submultiple of a sixth frequency (nf.sub.s) equal to the sum of the third frequency (f.sub.sO) and the fourth frequency (f.sub.

Abstract: The filter comprises four operational amplifiers in cascade, with switched capacitors in series at the input of every amplifier, with fixed capacitors in parallel to two of said amplifiers, with fixed and switched capacitors in parallel to the remaining amplifiers, and with fixed and switched capacitors in common to groups of several amplifiers in cascade. According to the invention, a path of fixed and switched capacitors in parallel connects the input of the filter to the input of the fourth amplifier, and a fixed capacitor connects the input of the filter to the input of the second amplifier.

Abstract: An integrated, low-pass filter of the first order made using the switched capacitors technique utilizes advantageously a single switched capacitor and only two switches in contrast to the filters of the prior art which utilize two switched capacitors and four switches. The filter of the invention requires a smaller integration area and moreover exhibits a greater precision of its DC gain.

Abstract: The TTL-compatible cell comprising two cascade coupled CMOS inverters is associated with an input pin of the integrated circuit to make it suitable to receive signals in TTL logic, as well as with a power-down pin, and is characterized in that said input (10) of the CMOS integrated circuit is connected to the input of the first of said two inverters (12, 14) through a first and a second respectively P-channel and N-channel MOS transistor in parallel (28, 30), the first controlled by the power-down pin (31), the second by an inverter (32) driven by said power-down pin, so as to be both off when the power-down signal is at logical 1 and active when the power-down signal is at logical 0. Between the input of the first inverter and the ground a further MOS transistor (34) is connected the gate whereof is controlled so that said further MOS transistor is active when the power-down signal is at logical 1 and is off when the power-down signal is at logical 0.

Abstract: The antibounce circuit comprises:(a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal;(b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate;(c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate;(d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.

Abstract: The amplification circuit comprises an operational amplifier and two groups of capacitances in input and feedback association with the operational amplifier. 2-phase switching means are periodically switched between a position in which two other capacitance groups are charged at output voltage values equal but opposite in sign and a position in which said other capacitances cancel each other out.

Abstract: A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediate signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.

Abstract: A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.

Abstract: A fully differential, CMOS, operational power amplifier, particularly useful as output buffer in monolithic analog subsystems, includes an input differential stage, two gain stages and two output stages. Each output stage may be individually provided with a functional feedback loop and locally compensated for reestablishing sufficient stability. An output common mode control circuit, operable in a continuous or sampled manner, is also contemplated, as well as a special circuit for controlling the DC biasing current through the output stages under rest conditions. The amplifier may be used indifferently as a balanced (differential) output or as a single-ended output amplifier without any depression of its performances.

Abstract: The circuit comprises a first and a second transistor provided with the sources coupled to one end of a supply voltage and the gates coupled to one another, and a third and fourth transistor provided with the sources coupled to the other end of the supply voltage, the gates coupled to one another, the drains coupled to the respective drains of said first and second transistor, and the gates of the first and of the fourth transistor being furthermore shorted each with its own gate. The coupling between the drains of the first and of the third transistor is constituted by a preset resistor to the ends of which the base and the emitter of a bipolar transistor are coupled having the collector of the bipolar transistor coupled to one end of the supply voltage. The four transistors may be replaced by respective pairs of transistors suitably coupled to each other.

Abstract: A CMOS output stage with large voltage swing particularly suited for output buffers in monolithic analog subsystems has two, push-pull connected, complementary MOS transistors and has feedback for improving its swing and linearity characteristics in comparison with those of the output stages without feedback of the prior art and also has sufficient stability characteristics which are re-established by local compensation. Furthermore the quiescent current is stabilized by a dedicated control circuit cooperating with a local feedback circuit.

Abstract: The amplifier comprises two like CMOS cascode circuits, each having a first and a second transistors with channels having a first plurality and a third and fourth transistors with channels having the opposite polarity, the drain of the first transistor being connected to the source of the second transistor, and the drain of the fourth transistor being connected to the source of the third transistor, the drains of the second and of the third transistors being connected to each other end composing one of the output terminals of the amplifier, the sources of the first transistors being connected to each other and to the drain of a fifth transistor with a channel having the first polarity, the source of which is fed by a first supply voltage, the sources of the fourth transistors of the two cascode circuits being fed by a second supply voltage.

Abstract: In a buffer with an operational amplifier having two inputs and two outputs and two feedback capacitances are inserted two other capacitances which in the measurement stage are switched in parallel to the feedback ones with opposite sign in such a manner as to cancel out the effects on the output voltage signal.