Patents by Inventor Gernot Fattinger

Gernot Fattinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018649
    Abstract: Compensation of on-die inductive parasitics in ladder filters through negative mutual inductance between ground inductors is disclosed herein. An exemplary ladder filter includes a primary arm of series resonators and two or more shunt resonator arms connecting nodes between the series resonators to ground. The resonators of the ladder filter are disposed over a semiconductor substrate, to form a circuit die. Constructed ladder filter dice may fail to achieve design filter rejection due to inductive parasitics (e.g., undesired magnetic induction between components). A first shunt arm and a second shunt arm are provided with mutual negatively coupled inductors in order to compensate for these parasitics and improve filter performance.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Yazid Yusuf, Mudar Al-Joumayly, Gernot Fattinger
  • Patent number: 11011498
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10964672
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 30, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Publication number: 20200358419
    Abstract: Compensation of on-die inductive parasitics in ladder filters through negative mutual inductance between ground inductors is disclosed herein. An exemplary ladder filter includes a primary arm of series resonators and two or more shunt resonator arms connecting nodes between the series resonators to ground. The resonators of the ladder filter are disposed over a semiconductor substrate, to form a circuit die. Constructed ladder filter dice may fail to achieve design filter rejection due to inductive parasitics (e.g., undesired magnetic induction between components). A first shunt arm and a second shunt arm are provided with mutual negatively coupled inductors in order to compensate for these parasitics and improve filter performance.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 12, 2020
    Inventors: Yazid Yusuf, Mudar Al-Joumayly, Gernot Fattinger
  • Patent number: 10804246
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 13, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10778180
    Abstract: Bulk Acoustic Wave (BAW) resonators that include a modified outside stack portion and methods for fabricating such BAW resonators are provided. One BAW resonator includes a reflector, a bottom electrode, a piezoelectric layer, and a top electrode. An active region is formed where the top electrode overlaps the bottom electrode and an outside region surrounds the active region. The piezoelectric layer includes a top surface adjacent to the top electrode and a bottom surface adjacent to the bottom electrode. The piezoelectric layer further includes an outside piezoelectric portion in the outside region with a bottom surface in the outside region that is an extension of the bottom surface of the piezoelectric layer, and the outside piezoelectric portion includes an angled sidewall that resides in the outside region and extends from the top surface of the piezoelectric layer to the bottom surface of the outside piezoelectric portion in the outside region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Alireza Tajic, Paul Stokes, Ralph Rothemund, Gernot Fattinger
  • Patent number: 10700732
    Abstract: Systems and methods relating to improving transmit (TX) port to receive (RX) port isolation of a duplexer or multiplexer are disclosed. In some embodiments, a system includes a duplexer or multiplexer having a transmit port, a receive port, and an antenna port. The system further includes a leakage cancellation subsystem adapted to cancel a leakage signal from the TX port of the duplexer or multiplexer to the RX port of the duplexer or multiplexer across a desired cancellation bandwidth. The leakage cancellation subsystem compensates for variation of the leakage signal across the desired cancellation bandwidth, thereby improving TX port to RX port isolation over conventional systems.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 30, 2020
    Assignee: Qorvo US, Inc.
    Inventor: Gernot Fattinger
  • Publication number: 20200150088
    Abstract: A fluidic device includes at least one bulk acoustic wave (BAW) resonator structure with a functionalized active region, and at least one first (inlet) port defined through a cover structure arranged over a fluidic passage containing the active region. At least a portion of the at least one inlet port is registered with the active region, permitting fluid to be introduced in a direction orthogonal to a surface of the active region bearing functionalization material. Such arrangement promotes mixing proximate to a BAW resonator structure surface, thereby reducing analyte stratification, increasing analyte binding rate, and reducing measurement time.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Gernot Fattinger, Rio Rivas
  • Patent number: 10615147
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10553564
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10533972
    Abstract: A fluidic device includes at least one bulk acoustic wave (BAW) resonator structure with a functionalized active region, and at least one first (inlet) port defined through a cover structure arranged over a fluidic passage containing the active region. At least a portion of the at least one inlet port is registered with the active region, permitting fluid to be introduced in a direction orthogonal to a surface of the active region bearing functionalization material. Such arrangement promotes mixing proximate to a BAW resonator structure surface, thereby reducing analyte stratification, increasing analyte binding rate, and reducing measurement time.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 14, 2020
    Assignee: QORVO US, INC.
    Inventors: Gernot Fattinger, Rio Rivas
  • Publication number: 20190378821
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 12, 2019
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, JR., Jon Chadwick
  • Publication number: 20190378819
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, JR., Jon Chadwick
  • Publication number: 20190305752
    Abstract: An acoustic resonator includes a first piezoelectric layer, a second piezoelectric layer, a coupler layer, a first electrode, and a second electrode. The first piezoelectric layer has a first polarity. The second piezoelectric layer has a second polarity opposite the first polarity. The coupler layer is between the first piezoelectric layer and the second piezoelectric layer. The first electrode is on the first piezoelectric layer opposite the coupler layer. The second electrode is on the second piezoelectric layer opposite the coupler layer.
    Type: Application
    Filed: March 1, 2019
    Publication date: October 3, 2019
    Inventors: Jyothi Swaroop Sadhu, Gernot Fattinger, Robert Aigner, Michael Schaefer
  • Patent number: 10205436
    Abstract: Embodiments of an acoustic wave filter system that includes at least one acoustic wave filter and acoustic wave tuning control circuitry are disclosed. The acoustic wave filter includes at least one acoustic wave resonator and defines a passband. To provide tuning for calibration or for dynamic filter operation, the acoustic wave tuning control circuitry is configured to bias one or more of the acoustic wave resonators with bias voltages. Biasing an acoustic wave resonator affects the resonances of the resonator, thereby allowing for the passband of the acoustic wave resonator to be tuned. Accordingly, the acoustic wave tuning control circuitry is configured to adjust the bias voltages so that the acoustic wave filter shifts the passband. In this manner, the passband of the acoustic wave filter can be tuned with high degree of accuracy and without requiring physical alterations to the acoustic wave resonators.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 12, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, Robert Aigner, Gernot Fattinger, George Maxim, Dirk Robert Walter Leipold, Nadim Khlat
  • Publication number: 20190044569
    Abstract: Systems and methods relating to improving transmit (TX) port to receive (RX) port isolation of a duplexer or multiplexer are disclosed. In some embodiments, a system includes a duplexer or multiplexer having a transmit port, a receive port, and an antenna port. The system further includes a leakage cancellation subsystem adapted to cancel a leakage signal from the TX port of the duplexer or multiplexer to the RX port of the duplexer or multiplexer across a desired cancellation bandwidth. The leakage cancellation subsystem compensates for variation of the leakage signal across the desired cancellation bandwidth, thereby improving TX port to RX port isolation over conventional systems.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 7, 2019
    Inventor: Gernot Fattinger
  • Patent number: 10097230
    Abstract: Systems and methods relating to improving transmit (TX) port to receive (RX) port isolation of a duplexer or multiplexer are disclosed. In some embodiments, a system includes a duplexer or multiplexer having a transmit port, a receive port, and an antenna port. The system further includes a leakage cancellation subsystem adapted to cancel a leakage signal from the TX port of the duplexer or multiplexer to the RX port of the duplexer or multiplexer across a desired cancellation bandwidth. The leakage cancellation subsystem compensates for variation of the leakage signal across the desired cancellation bandwidth, thereby improving TX port to RX port isolation over conventional systems.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 9, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Gernot Fattinger
  • Patent number: 10009052
    Abstract: RF filtering circuitry includes a first transmit signal node, a second transmit signal node, a common node, first transmit signal filtering circuitry, second transmit signal filtering circuitry, and transmit signal cancellation circuitry. The first transmit signal filtering circuitry is coupled between the first transmit signal node and the common node and is configured to pass RF transmit signals within a first transmit signal frequency band while attenuating signals outside the first transmit signal frequency band. The second transmit signal filtering circuitry is coupled between the second transmit signal node and the common node and is configured to pass RF transmit signals within a second transmit signal frequency band while attenuating signals outside the second transmit signal frequency band. The transmit signal cancellation circuitry is coupled between the common node and the second transmit signal node and is configured to generate a transmit cancellation signal.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 26, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Gernot Fattinger, Marcus Granger-Jones, Robert Aigner
  • Patent number: 9948272
    Abstract: Embodiments of a Bulk Acoustic Wave (BAW) device including a high conductivity electrode are disclosed. In some embodiments, a BAW device includes a piezoelectric layer, a first electrode on a first surface of the piezoelectric layer, and a second electrode on a second surface of the piezoelectric layer opposite the first electrode. The second electrode includes a first metal layer and a second metal layer. The second metal layer is on the second surface of the piezoelectric layer, and the first metal layer is over a surface of the second metal layer opposite the piezoelectric layer, where the first metal layer is separated from the second metal layer by an air gap. By including the air gap, the thickness of the first metal layer (e.g., a high conductivity layer) can be increased to thereby increase the electrical conductivity of the second electrode while maintaining the performance of the BAW device.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 17, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Paul Stokes, Gernot Fattinger
  • Publication number: 20180097507
    Abstract: Embodiments of an acoustic wave filter system that includes at least one acoustic wave filter and acoustic wave tuning control circuitry are disclosed. The acoustic wave filter includes at least one acoustic wave resonator and defines a passband. To provide tuning for calibration or for dynamic filter operation, the acoustic wave tuning control circuitry is configured to bias one or more of the acoustic wave resonators with bias voltages. Biasing an acoustic wave resonator affects the resonances of the resonator, thereby allowing for the passband of the acoustic wave resonator to be tuned. Accordingly, the acoustic wave tuning control circuitry is configured to adjust the bias voltages so that the acoustic wave filter shifts the passband. In this manner, the passband of the acoustic wave filter can be tuned with high degree of accuracy and without requiring physical alterations to the acoustic wave resonators.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 5, 2018
    Inventors: Baker Scott, Robert Aigner, Gernot Fattinger, George Maxim, Dirk Robert Walter Leipold, Nadim Khlat