Patents by Inventor Gerrit Jan Hemink

Gerrit Jan Hemink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11101326
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 24, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 11088206
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 10, 2021
    Assignee: SanDisk Tehnologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 11081198
    Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 3, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Publication number: 20210233589
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Patent number: 11011242
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 18, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
  • Patent number: 10978145
    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Biswajit Ray, Peter Rabkin, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
  • Patent number: 10978156
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Publication number: 20210050054
    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Biswajit Ray, Peter Rabkin, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
  • Patent number: 10910083
    Abstract: A memory array with a fabrication joint includes a controller configured to apply a detection voltage on a word line coupled to a plurality of bitlines, count a number of bitlines having a first type of response to the detection voltage, and on condition that the number of bitlines exceeds a configured value, program memory cells on at least one dummy word line adjacent to the fabrication joint with a particular threshold voltage.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 2, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Publication number: 20200410037
    Abstract: An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Federico Nardi, Gerrit Jan Hemink, Won Ho Choi
  • Publication number: 20200365221
    Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Publication number: 20200365220
    Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Patent number: 10839928
    Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Publication number: 20200311512
    Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
  • Publication number: 20200303459
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
  • Publication number: 20200294615
    Abstract: A memory array with a fabrication joint includes a controller configured to apply a detection voltage on a word line coupled to a plurality of bitlines, count a number of bitlines having a first type of response to the detection voltage, and on condition that the number of bitlines exceeds a configured value, program memory cells on at least one dummy word line adjacent to the fabrication joint with a particular threshold voltage.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Xiang Yang, Gerrit Jan Hemink
  • Patent number: 10748622
    Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 18, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Lei Lin, Zhuojie Li, Tai-Yuan Tseng, Henry Chin, Gerrit Jan Hemink
  • Publication number: 20200234768
    Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
    Type: Application
    Filed: February 22, 2019
    Publication date: July 23, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Lei Lin, Zhuojie Li, Tai-Yuan Tseng, Henry Chin, Gerrit Jan Hemink
  • Publication number: 20200227125
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
  • Patent number: 10643720
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li