Patents by Inventor Gerrit Jan Hemink
Gerrit Jan Hemink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200227125Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.Type: ApplicationFiled: March 25, 2020Publication date: July 16, 2020Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
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Patent number: 10643720Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.Type: GrantFiled: May 23, 2018Date of Patent: May 5, 2020Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
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Patent number: 10573395Abstract: Non-volatile memory strings, which are coupled to respective bit lines and source lines, may include multiple non-volatile memory cells coupled to respective word lines. Multiple sensing operations may be used to determine data programmed into a particular non-volatile memory cell. For example, a control circuit may sense multiple values from a particular non-volatile memory cell included in a non-volatile memory string using different voltage levels on a source line coupled to the non-volatile memory string. The control circuit may select one of the multiple values based on a program state of a different non-volatile memory cell adjacent to the particular non-volatile memory cell.Type: GrantFiled: November 30, 2018Date of Patent: February 25, 2020Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Gerrit Jan Hemink
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Publication number: 20200034697Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.Type: ApplicationFiled: March 28, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
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Patent number: 10535412Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.Type: GrantFiled: April 26, 2018Date of Patent: January 14, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta, Jianzhi Wu, Gerrit Jan Hemink
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Publication number: 20200005871Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Applicant: SanDisk Technologies LLCInventors: Xiang YANG, Aaron LEE, Gerrit Jan HEMINK, Ken OOWADA, Toru MIWA
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Publication number: 20190362799Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.Type: ApplicationFiled: May 23, 2018Publication date: November 28, 2019Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
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Publication number: 20190252030Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.Type: ApplicationFiled: April 26, 2018Publication date: August 15, 2019Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta, Jianzhi Wu, Gerrit Jan Hemink
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Patent number: 10374014Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: GrantFiled: January 12, 2018Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
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Patent number: 10304551Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.Type: GrantFiled: June 27, 2016Date of Patent: May 28, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Biswajit Ray, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
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Publication number: 20190115072Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: ApplicationFiled: January 12, 2018Publication date: April 18, 2019Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
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Publication number: 20190115391Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: ApplicationFiled: January 12, 2018Publication date: April 18, 2019Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
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Publication number: 20190115071Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: ApplicationFiled: January 12, 2018Publication date: April 18, 2019Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
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Patent number: 10262730Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: GrantFiled: January 12, 2018Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
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Patent number: 10008273Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.Type: GrantFiled: June 13, 2016Date of Patent: June 26, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
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Publication number: 20170372789Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Applicant: SanDisk Technologies LLCInventors: Biswajit Ray, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
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Publication number: 20170358365Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Applicant: SanDisk Technologies LLCInventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
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Patent number: 9805809Abstract: Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising a plurality of word lines. A controller is configured to perform a read operation on one or more word lines adjacent to a target word line. A controller is configured to determine a read setting for application to a target word line based on a result of a read operation on one or more word lines adjacent to the target word line. A controller is configured to perform a read operation on a target word line using a determined read setting.Type: GrantFiled: August 31, 2016Date of Patent: October 31, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenming Zhou, Guirong Liang, Gerrit Jan Hemink, Dana Lee, Chandu Gorla, Sarath Puthenthermadam, Deepanshu Dutta
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Patent number: 9564226Abstract: Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.Type: GrantFiled: October 30, 2015Date of Patent: February 7, 2017Assignee: SanDisk Technologies LLCInventors: Mohan Dunga, Gerrit Jan Hemink, Zhenming Zhou, Masaaki Higashitani
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Patent number: 9548124Abstract: A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary, resulting in widened threshold voltage distributions. In one approach, a programming parameter is optimized for each word line based on a measurement of the threshold voltage distributions in an initial programming operation. An adjustment to the programming parameter of a word line can be based, e.g., on measurements from adjacent word lines, and a position of the word line in a set of word lines. The programming parameter can include a programming mode such as a number of programming passes. Moreover, the programming parameters from one set of word lines can be used for another set of word lines having a similar physical layout due to the variations in the fabrication process.Type: GrantFiled: October 14, 2015Date of Patent: January 17, 2017Assignee: SanDisk Technologies LLCInventors: Arash Hazeghi, Gerrit Jan Hemink, Dana Lee, Henry Chin, Bo Lei, Zhenming Zhou