Patents by Inventor Gerrit Willem Den Besten
Gerrit Willem Den Besten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10284180Abstract: A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.Type: GrantFiled: June 9, 2017Date of Patent: May 7, 2019Assignee: NXP B.V.Inventor: Gerrit Willem den Besten
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Publication number: 20180358953Abstract: A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Inventor: Gerrit Willem den Besten
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Patent number: 9467312Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.Type: GrantFiled: March 10, 2014Date of Patent: October 11, 2016Assignee: NXP B.V.Inventors: Marcello Ganzerli, Gerrit Willem den Besten
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Patent number: 9419515Abstract: A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages.Type: GrantFiled: March 7, 2014Date of Patent: August 16, 2016Assignee: NXP B.V.Inventor: Gerrit Willem den Besten
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Patent number: 9379694Abstract: A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal.Type: GrantFiled: December 9, 2011Date of Patent: June 28, 2016Assignee: NXP B.V.Inventor: Gerrit Willem den Besten
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Publication number: 20150256063Abstract: A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: NXP B.V.Inventor: Gerrit Willem den Besten
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Publication number: 20150256362Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.Type: ApplicationFiled: March 10, 2014Publication date: September 10, 2015Applicant: NXP B.V.Inventors: Marcello Ganzerli, Gerrit Willem den Besten
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Patent number: 9031153Abstract: A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period.Type: GrantFiled: November 12, 2008Date of Patent: May 12, 2015Assignee: NXP B.V.Inventor: Gerrit Willem Den Besten
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Patent number: 9025288Abstract: Cross-talk is mitigated in a switching circuit. In accordance with one or more embodiments, an apparatus includes a multi-pin connector having signal-carrying electrodes that communicate with a device external to the apparatus, and respective field-effect switches that couple the signal-carrying electrodes to respective communication channels in the apparatus. The switches include a first field-effect semiconductor switch having a gate electrode adjacent a channel region that connects electrodes (e.g., source and drain regions) when a threshold switching voltage is applied to the gate, in which the electrodes are connected between one of the signal-carrying electrodes and a first channel coupled to an electrostatic discharge (ESD) circuit. A bias circuit mitigates cross-talk between the communication channels by biasing the channel region of the first field-effect semiconductor switch (in an off state) to boost the threshold switching voltage over a threshold discharge voltage of the ESD circuit.Type: GrantFiled: March 15, 2013Date of Patent: May 5, 2015Assignee: NXP B.V.Inventors: Madan Vemula, James Caravella, James Spehar, Gerrit Willem den Besten
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Publication number: 20140266394Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Gerrit Willem den Besten, Madan Vemula, Jingsong Zhou
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Publication number: 20140268445Abstract: Cross-talk is mitigated in a switching circuit. In accordance with one or more embodiments, an apparatus includes a multi-pin connector having signal-carrying electrodes that communicate with a device external to the apparatus, and respective field-effect switches that couple the signal-carrying electrodes to respective communication channels in the apparatus. The switches include a first field-effect semiconductor switch having a gate electrode adjacent a channel region that connects electrodes (e.g., source and drain regions) when a threshold switching voltage is applied to the gate, in which the electrodes are connected between one of the signal-carrying electrodes and a first channel coupled to an electrostatic discharge (ESD) circuit. A bias circuit mitigates cross-talk between the communication channels by biasing the channel region of the first field-effect semiconductor switch (in an off state) to boost the threshold switching voltage over a threshold discharge voltage of the ESD circuit.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: NXP B.V.Inventors: Madan Vemula, James Caravella, James Spehar, Gerrit Willem den Besten
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Patent number: 8836408Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.Type: GrantFiled: March 15, 2013Date of Patent: September 16, 2014Assignee: NXP B.V.Inventors: Gerrit Willem den Besten, Madan Vemula, Jingsong Zhou
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Patent number: 8811557Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.Type: GrantFiled: December 15, 2011Date of Patent: August 19, 2014Assignee: NXP B.V.Inventors: Gerrit Willem den Besten, Arnoud Pieter van der Wel
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Patent number: 8433000Abstract: The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.Type: GrantFiled: November 28, 2007Date of Patent: April 30, 2013Assignee: NXP B.V.Inventors: Gerrit Willem Den Besten, Erwin Janssen
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Patent number: 8396105Abstract: An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.Type: GrantFiled: September 12, 2006Date of Patent: March 12, 2013Assignee: NXP B.V.Inventors: Friedel Gerfers, Gerrit Willem Den Besten, Pavel Petkov, Andreas Koellmann, Jim E. Conder
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Publication number: 20120286846Abstract: A switching circuit employs switches operating at low on resistance and high off capacitance. In connection with various example embodiments, a switching circuit selectively couples a communication port to one of two or more internal circuits based upon a type of input at the communication port. A sensor circuit senses the type of the input and, based upon the sensed input type, actuates one or more switches in the switching circuit.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Inventors: Olaf Wunnicke, Willem Frederik Adrianus Besling, Gerrit Willem den Besten, Michael Joehren, Klaus Reimann, James Raymond Spehar, Peter Gerard Steeneken
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Publication number: 20120286588Abstract: A switching circuit employs MEMS devices. In connection with various example embodiments, signal switching circuit couples primary and secondary data link connectors having at least two channels and an electrode for each channel. A MEMS switch is coupled to each channel in of the secondary data link connectors, and includes a suspended membrane, first and second contact electrodes (one being in the membrane) and a biasing circuit that biases the membrane for moving the membrane between open and closed positions to contact the electrodes. A switch controller circuit selectively controls the application of an actuation voltage to each of the biasing circuits, thereby selectively actuating the membranes between the open and closed positions for routing signals between the primary and secondary data link connectors.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: NXP B.V.Inventors: Peter Steeneken, Olaf Wunnicke, Klaus Reimann, James Raymond Spehar, Michael Joehren, Gerrit Willem den Besten
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Publication number: 20120154059Abstract: A multi-phase clock and data recovery circuit system including a voltage controlled oscillator including plural identical structural cells coupled in a ring, the voltage controlled oscillator providing plural phased shifted signals having the same frequency. The circuit further includes a feedback loop including plural data samplers adapted to receive the plural phase shifted signals provided by the voltage controlled oscillator and a phase detector coupled to coupled to a phase alignment circuit receiving output signals generated by the plural data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Applicant: NXP B.V.Inventors: Arnoud Pieter van der Wel, Gerrit Willem den Besten
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Publication number: 20120155589Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Applicant: NXP B.V.Inventors: Gerrit Willem den Besten, Arnoud Pieter van der Wel
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Publication number: 20120146705Abstract: A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal.Type: ApplicationFiled: December 9, 2011Publication date: June 14, 2012Applicant: NXP B.V.Inventor: Gerrit Willem Den Besten