Abstract: An integrated circuit for emulating a resistor is based on the output resistance of a non-linear circuit element, such as a transistor. In the case of a transistor, it is biased into operation in its linear region, and a voltage dependent on the ac source-drain voltage is coupled to the gate voltage, thereby to improve linearity of the drain-source resistance with respect to the drain-source voltage. This modification to the gate voltage can be used to alter the transfer function such that the drain-source resistance is no longer dependent on the drain-source voltage.

Abstract: There is provided a method of operating a communications system comprising a transmitting station and a receiving station, the method in the transmitting station comprising encoding a clock signal with data to form encoded signals for transmission; transmitting the encoded signals to the receiving station; the method in the receiving station comprising decoding the encoded signals to extract the clock signal and data; processing the data under the control of the decoded clock signal. The method further comprises, when no data is required to be transmitted to the receiving station, transmitting further encoded signals to the receiving station in order for the receiving station to decode the further encoded signals and extract a clock signal.

Abstract: A frequency divider (200; 300; 400) configured to receive a plurality of oscillating signals (202; 302; 402) and generate output signalling (204; 310; 410). The frequency divider comprises an enable signalling generator (206) configured to process the plurality of oscillating signals (202; 302; 402) and generate enable signalling (210; 314) representative of which of the oscillating signals (202; 302; 402) is to be used to derive the output signalling (204; 310; 410). The frequency divider also comprises an output signal selector (208; 308; 408) configured to process one or more of the oscillating signals (202; 302; 402) and the enable signalling (210; 314) such that an oscillating signal (202; 302; 402) is provided as the output signalling (204; 310; 410) of the frequency divider in accordance with the enable signalling (210; 314).

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period.

Abstract: The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

Abstract: An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: There is provided a method of operating a communications system comprising a transmitting station and a receiving station, the method in the transmitting station comprising encoding a clock signal with data to form encoded signals for transmission; transmitting the encoded signals to the receiving station; the method in the receiving station comprising decoding the encoded signals to extract the clock signal and data; processing the data under the control of the decoded clock signal. The method further comprises, when no data is required to be transmitted to the receiving station, transmitting further encoded signals to the receiving station in order for the receiving station to decode the further encoded signals and extract a clock signal.

Abstract: Power supply connections to an integrated circuit are tested. The power supply connections are connected to a power supply conductor in the integrated circuit. For the test, combinations of current drawing circuits are switched on near the point where the power supply connection under test is connected to the power supply conductor. The current drawing circuits draw a considerable current, so as to cause a detectable voltage drop over the power supply connection, if this connection is operational. Different subsets of the current drawing circuits are activated successively. To prevent that all of the current drawing circuits are switched on at the same time by error, activation of each subset is controlled by a signal indicative of completion of activation of the preceding subset. A respective signal line is provided for each subset, to provide the signal for the subset.

Abstract: Integrated circuit with a test interface for testing a conductive connection between a supply pad and a supply of a functional block in the integrated circuit. A current test circuit has test inputs coupled to a first and a second point along the conductive connection, for comparing a voltage across the test inputs with a threshold. The current test circuit contains a threshold shifting circuit for shifting the threshold to a shifted value dependent on a voltage across the test inputs when the threshold shifting circuit is active. Testing is executed in two steps, making the threshold shifting circuit active when a first voltage is applied across test inputs and comparing a second voltage at the test input with the shifted threshold. One of the first and second voltage is a voltage drop across the connection when the integrated circuit is set to draw current along a connection, the other one of the first and second voltage is a reference voltage.

Abstract: An electronic circuit comprising a frequency or phase-locked loop (PLL) comprising a first input terminal (1) coupled to receive a first input signal (D); a second input terminal (2) coupled to receive a second input signal (CLK); detection means (DMNS) for comparing the frequency or phase of the first input signal (D) with the frequency or phase of the second input signal (CLK), respectively, and for supplying directly or via a charge pump (CHPPMP) a control voltage (Vcntrl) as a result of the comparison of the first (D) and second (CLK) input signals; a control transistor (T0) having a first main terminal and a control terminal which are coupled to receive the control voltage (Vcntrl) and having a second main terminal for supplying a control current (Icntrl) responsive to the control voltage (Vcntrl); a capacitor (C) coupled in between the first main terminal and the control terminal; a current controlled oscillator (CCO) having an input terminal (CCOI) coupled to receive the control current (Icntrl) and ha

Abstract: A station in a communication bus system is connected to a signal transmission line. The station contains a wave splitter coupled to the transmission line and a transmission section coupled to an input of the wave splitter for transmitting an outgoing wave signal to travel out over the transmission line from the wave splitter. The station contains a reception section coupled to an output of the wave splitter for receiving an incoming wave signal that travels into the wave splitter from the connector. The station has a control unit being arranged to operate in different control modes, according to the presence or absence of a further apparatus connected to the transmission line, dependent on whether the reception section does not detect or does detect a reflection of a wave transmitted by the transmission section, respectively.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: Power supply connections to an integrated circuit are tested. The power supply connections are connected to a power supply conductor in the integrated circuit. For the test, combinations of current drawing circuits are switched on near the point where the power supply connection under test is connected to the power supply conductor. The current drawing circuits draw a considerable current, so as to cause a detectable voltage drop over the power supply connection, if this connection is operational. Different subsets of the current drawing circuits are activated successively. To prevent that all of the current drawing circuits are switched on at the same time by error, activation of each subset is controlled by a signal indicative of completion of activation of the preceding subset. A respective signal line is provided for each subset, to provide the signal for the subset.

Abstract: A station in a communication bus system, is connected to a signal transmission line. The station contain a wave splitter coupled to the transmission line and a transmission section coupled to an input of the wave splitter for transmitting an outgoing wave signal to travel out over the transmission line from the wave splitter. The station contains a reception section coupled to an output of the wave splitter for receiving an incoming wave signal that travels into the wave splitter from the connector. The station has a control unit being arranged to operate in different control modes, according to the presence or absence of a further apparatus connected to the transmission line, dependent on whether the reception section does not detect or does detect a reflection of a wave transmitted by the transmission section respectively.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: Integrated circuit with a test interface for testing a conductive connection between a supply pad and a supply of a functional block in the integrated circuit. A current test circuit has test inputs coupled to a first and a second point along the conductive connection, for comparing a voltage across the test inputs with a threshold. The current test circuit contains a threshold shifting circuit for shifting the threshold to a shifted value dependent on a voltage across the test inputs when the threshold shifting circuit is active. Testing is executed in two steps, making the threshold shifting circuit active when a first voltage is applied across test inputs and comparing a second voltage at the test input with the shifted threshold. One of the first and second voltage is a voltage drop across the connection when the integrated circuit is set to draw current along said connection, the other one of the first and second voltage is a reference voltage.