Patents by Inventor Gert Leusink
Gert Leusink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8722548Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.Type: GrantFiled: September 24, 2010Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
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Patent number: 8580034Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma in the vacuum processing tool. The Si layer is exposed to the soft plasma to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and an Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: GrantFiled: March 31, 2006Date of Patent: November 12, 2013Assignee: Tokyo Electron LimitedInventor: Gert Leusink
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Patent number: 8460945Abstract: A method and system are provided for monitoring status of a system component in a process chamber of a batch type processing system. The method includes exposing a system component to light from a light source and monitoring interaction of the light with the system component to determine status of the system component. The method can detect light transmission and/or light reflection from a system component during a process that can include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, and a liner, and can further contain a protective coating.Type: GrantFiled: September 30, 2003Date of Patent: June 11, 2013Assignee: Tokyo Electron LimitedInventors: David L. O'Meara, Daniel Craig Burdett, Stephen H. Cabral, Gert Leusink, John William Kostenko, Cory Wajda
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Patent number: 8168548Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and exposing the Si-containing layer to oxidation radicals in an UV-assisted oxidation process to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and a Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: GrantFiled: September 29, 2006Date of Patent: May 1, 2012Assignee: Tokyo Electron LimitedInventor: Gert Leusink
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Publication number: 20120074533Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Applicants: Tokyo Electron (TEL)Limited, International Business Machines CorporationInventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
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Patent number: 7674710Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.Type: GrantFiled: November 20, 2006Date of Patent: March 9, 2010Assignee: Tokyo Electron LimitedInventors: Shigeo Ashigaki, Hideaki Yamasaki, Tomoyuki Sakoda, Mikio Suzuki, Genji Nakamura, Gert Leusink
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Patent number: 7479454Abstract: A method and system for monitoring status of a system component during a process. The method includes exposing a system component to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component. Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, an injector, a substrate holder, a liner, a pedestal, a cap cover, an electrode, and a heater, any of which can further include a protective coating.Type: GrantFiled: September 30, 2003Date of Patent: January 20, 2009Assignee: Tokyo Electron LimitedInventors: David L. O'Meara, Daniel Craig Burdett, Stephen H. Cabral, Gert Leusink, John William Kostenko, Cory Wajda
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Patent number: 7419702Abstract: A method for processing a substrate on a ceramic substrate heater in a process chamber. The method includes forming a protective coating on the ceramic substrate heater in the process chamber and processing a substrate on the coated substrate heater. The processing can include providing a substrate to be processed on the coated ceramic substrate heater, performing a process on the substrate by exposing the substrate to a process gas, and removing the processed substrate from the process chamber.Type: GrantFiled: March 31, 2004Date of Patent: September 2, 2008Assignees: Tokyo Electron Limited, International Business Machines Corp.Inventors: Kazuhito Nakamura, Cory Wajda, Enrico Mosca, Yumiko Kawano, Gert Leusink, Fenton R. McFeely, Sandra G. Malhotra
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Patent number: 7393761Abstract: A method for treating a gate stack in the fabrication of a semiconductor device by providing a substrate containing a gate stack having a dielectric layer formed on the substrate and a metal-containing gate electrode layer formed on the high-k dielectric layer, forming low-energy excited dopant species from a process gas in a plasma, and exposing the gate stack to the excited dopant species to incorporate a dopant into the gate stack. The method can be utilized to tune the workfunction of the gate stack.Type: GrantFiled: January 31, 2005Date of Patent: July 1, 2008Assignee: Tokyo Electron LimitedInventors: Cory Wajda, Gert Leusink
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Publication number: 20080119033Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.Type: ApplicationFiled: November 20, 2006Publication date: May 22, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Shigeo Ashigaki, Hideaki Yamasaki, Tomoyuki Sakoda, Mikio Suzuki, Genji Nakamura, Gert Leusink
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Publication number: 20080078987Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and exposing the Si-containing layer to oxidation radicals in an UV-assisted oxidation process to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and a Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Gert Leusink
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Patent number: 7300891Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to electro-magnetic (EM) radiation, such as EM radiation having a wavelength component less than about 500 nm. The EM source can include a multi-frequency source of radiation. Additionally, the source of radiation is collimated in order to selectively treat regions of a non-planar film.Type: GrantFiled: March 29, 2005Date of Patent: November 27, 2007Assignee: Tokyo Electron, Ltd.Inventors: Igeta Masonobu, Cory Wajda, Gert Leusink
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Publication number: 20070238268Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma in the vacuum processing tool. The Si layer is exposed to the soft plasma to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and an Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: TOKYO ELECTRON LIMITEDInventor: Gert Leusink
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Patent number: 7265066Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to collimated electro-magnetic (EM) radiation to anisotropically expose the film. The EM radiation can have a component having a wavelength less than about 500 nm. The EM source can include a multi-frequency source of radiation.Type: GrantFiled: March 29, 2005Date of Patent: September 4, 2007Assignee: Tokyo Electron, Ltd.Inventors: Igeta Masonobu, Cory Waida, Gert Leusink
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Publication number: 20060226518Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to electromagnetic (EM) radiation, such as EM radiation having a wavelength component less than about 500 nm. The EM source can include a multi-frequency source of radiation. Additionally, the source of radiation is collimated in order to selectively treat regions of a non-planar film.Type: ApplicationFiled: March 29, 2005Publication date: October 12, 2006Inventors: Igeta Masanobu, Cory Wajda, Gert Leusink
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Publication number: 20060226519Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to collimated electro-magnetic (EM) radiation to anisotropically expose the film. The EM radiation can have a component having a wavelength less than about 500 nm. The EM source can include a multi-frequency source of radiation.Type: ApplicationFiled: March 29, 2005Publication date: October 12, 2006Inventors: Igeta Masonobu, Cory Waida, Gert Leusink
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Publication number: 20060172474Abstract: A method for treating a gate stack in the fabrication of a semiconductor device by providing a substrate containing a gate stack having a dielectric layer formed on the substrate and a metal-containing gate electrode layer formed on the high-k dielectric layer, forming low-energy excited dopant species from a process gas in a plasma, and exposing the gate stack to the excited dopant species to incorporate a dopant into the gate stack. The method can be utilized to tune the workfunction of the gate stack.Type: ApplicationFiled: January 31, 2005Publication date: August 3, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Cory Wajda, Gert Leusink
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Publication number: 20060068098Abstract: A method for depositing a Ru metal layer on a substrate is presented. The method includes providing a substrate in a process chamber, introducing a process gas in the process chamber in which the process gas comprises a carrier gas, a ruthenium-carbonyl precursor, and hydrogen. The method further includes depositing a Ru metal layer on the substrate by a thermal chemical vapor deposition process. In one embodiment of the invention, the ruthenium-carbonyl precursor can contain Ru3(CO)12. and the Ru metal layer can be deposited at a substrate temperature resulting in the Ru metal layer having predominantly Ru(002) crystallographic orientation.Type: ApplicationFiled: September 27, 2004Publication date: March 30, 2006Applicant: Tokyo Electron LimitedInventors: Hideaki Yamasaki, Yumiko Kawano, Gert Leusink
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Publication number: 20060068588Abstract: A method for depositing Ru and Re metal layers on substrates with high deposition rates, low particulate contamination, and good step coverage on patterned substrates is presented. The method includes providing a substrate in a process chamber, introducing a process gas in the process chamber in which the process gas comprises a carrier gas and a metal precursor selected from the group consisting of a ruthenium-carbonyl precursor and a rhenium-carbonyl precursor. The method further includes depositing a Ru or Re metal layer on the substrate by a thermal chemical vapor deposition process at a process chamber pressure less than about 20 mTorr.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: Hideaki Yamasaki, Kenji Suzuki, Emmanuel Guidotti, Enrico Mosca, Gert Leusink, Yumiko Kawano, Fenton McFeely, Sandra Malhotra
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Publication number: 20060068097Abstract: A method for forming a passivated metal layer that preserves the properties and morphology of an underlying metal layer during subsequent exposure to oxygen-containing ambients. The method includes providing a substrate in a process chamber, exposing the substrate to a process gas containing a rhenium-carbonyl precursor to deposit a rhenium metal layer on the substrate in a chemical vapor deposition process, and forming a passivation layer on the rhenium metal layer to thereby inhibit oxygen-induced growth of rhenium-containing nodules on the rhenium metal surface.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hideaki Yamasaki, Kazuhito Nakamura, Yumiko Kawano, Gert Leusink, Fenton McFeely, Paul Jamison