Abstract: A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure includes a lower silicon substrate and an upper silicon pattern electrically insulated from the lower silicon pattern by an isolating insulation layer buried by a reverse T-type hole formed in the lower silicon substrate. A gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source/drain regions are formed in the upper silicon pattern centered around the gate electrode. Also, a channel region is disposed between the source/drain region. A silicon layer or a porous silicon layer is formed under the channel region for electrically connecting the lower silicon substrate and the upper silicon pattern. A body contact, which is the same as that of a general semiconductor device, is thus allowed without a special change in the design of the semiconductor device.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch mask, forming an impurity layer in or on a bottom surface of the first trench, forming a second trench exposing a buried oxide layer in the SOI layer in the remainder of the isolation layer region except the portion thereof between the element region and the ground region, and forming an isolation layer by depositing an insulation layer over the SOI substrate having the first and second trenches. The impurity layer can be formed by depositing a SiGe single crystal layer in the bottom surface of the first trench. Also, the impurity layer can be formed by implanting ions in the bottom surface of the first trench.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion.

Abstract: A method of forming a single crystalline silicon pattern using a structural selective epitaxial growth technique and a selective silicon etching technique, wherein an insulating layer pattern is formed on a semiconductor substrate; polycrystalline silicon is grown on the insulating layer pattern and simultaneously, single crystalline silicon is grown on the semiconductor substrate between the insulating layer patterns. Then, the polycrystalline silicon is removed from the insulating layer pattern. Preferably, the growing of the silicon is performed at a temperature of between about 700 to about 750° C. and a pressure of between about 5 to about 200 Torr. Removing the polycrystalline silicon is performed at a temperature of between about 700 to about 800° C. employing an etch recipe in which polycrystalline silicon has a faster etching rate than single crystalline silicon.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure includes a lower silicon substrate and an upper silicon pattern electrically insulated from the lower silicon pattern by an isolating insulation layer buried by a reverse T-type hole formed in the lower silicon substrate. A gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source/drain regions are formed in the upper silicon pattern centered around the gate electrode. Also, a channel region is disposed between the source/drain region. A silicon layer or a porous silicon layer is formed under the channel region for electrically connecting the lower silicon substrate and the upper silicon pattern. A body contact, which is the same as that of a general semiconductor device, is thus allowed without a special change in the design of the semiconductor device.

Abstract: A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion.

Abstract: A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch mask, forming an impurity layer in or on a bottom surface of the first trench, forming a second trench exposing a buried oxide layer in the SOI layer in the remainder of the isolation layer region except the portion thereof between the element region and the ground region, and forming an isolation layer by depositing an insulation layer over the SOI substrate having the first and second trenches. The impurity layer can be formed by depositing a SiGe single crystal layer in the bottom surface of the first trench. Also, the impurity layer can be formed by implanting ions in the bottom surface of the first trench.