Abstract: A memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. A first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. A second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. The first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

Abstract: Disclosed in an intravascular ultrasound (IVUS) image analysis method, comprising the steps of: allowing a computer to acquire an IVUS image of an object; segmenting a constituent element included in the IVUS image; and determining the constituent parts and the degree of risk of plaque included in the IVUS image.

Abstract: The present technology includes a memory device and a method of manufacturing the memory device. The memory device includes a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated, a word line included in the memory block, a first drain selection line included in the memory block and positioned on the word line, a first drain contact contacting the first drain selection line of the first connection region, a second drain contact contacting the first drain selection line of the second connection region, and a first drain voltage supply line commonly contacting the first and second drain contacts.

Abstract: A memory device may include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked along a first direction, an opening extending in the first direction from at least one conductive layer, among the plurality of conductive layers, in the stack structure, and a contact plug in the opening. The opening may include a protrusion portion protruding in a second direction intersecting the first direction.

Abstract: A semiconductor memory device may include includes a bit line and a back gate strap line extending on a substrate, an active pattern on the bit line and the back gate strap line, a word line on a first side wall of the active pattern, a back gate electrode on a second side wall of the active pattern and connected to the back gate strap line, a data storage pattern connected to a face of the active pattern, and a word line contact plug connected to the word line. A first face of the back gate electrode and a first face of the word line may face the bit line and the back gate strap line. The first face of the back gate electrode may be connected to the back gate strap line. A second face of the word line may be connected to the word line contact plug.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

Abstract: The present disclosure provides imidazolyl compounds of Formula (I) and methods of preparing the compounds. The provided compounds are able to bind protein kinases and may be useful in modulating (e.g., inhibiting) the activity of a protein kinase in a subject or cell and/or in treating or preventing a disease (e.g., proliferative disease, genetic disease, hematological disease, neurological disease, painful condition, psychiatric disorder, or metabolic disorder) in a subject in need thereof. Also provided are pharmaceutical compositions, kits, methods, and uses that include or involve a compound described herein.

Abstract: A memory device may include: a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked along a first direction, the stack structure including a cell region and a contact region, the contact region extending from the cell region and having a stepped structure; a plurality of contact plugs respectively in contact with the plurality of conductive layers in the contact region, the plurality of contact plugs extending in the first direction; and a plurality of lower pillars respectively in contact with the contact plugs, the plurality of lower pillars being located on the bottom of the contact plugs in the stack structure. Each of the plurality of lower pillars may include a liner layer in contact with the stack structure, and a pillar structure surrounded by the liner layer.

Abstract: A semiconductor device, and a method of manufacturing the same, includes a gate stack including a plurality of conductive lines extending in a first horizontal direction, a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction, and a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.

Abstract: A memory device, and a method of manufacturing the same, includes a first select line including a first cell area, a second select line including a second cell area disposed in a first direction from the first cell area, a first separation pattern extending in a second direction intersecting the first direction between the first cell area and the second cell area, second separation patterns extending from both ends of the first separation pattern in the first direction and a third direction opposite the first direction, respectively, and a third separation pattern extending from at least one of the second separation patterns in the second direction, and disposed in a direction opposite the first separation pattern with respect to the at least one second separation pattern.

Abstract: A mounting plate and a cover assembly for a steering wheel, which cover assembly includes the mounting plate, are provided. The mounting plate is configured so that a hook of the mounting plate does not directly press an inner cover of the cover assembly. The mounting plate includes a plate body provided to form an exterior of the mounting plate, the hook being configured to protrude from an outer surface of the plate body to penetrate an outer cover and the inner cover of the cover assembly. A rib is also provided which is configured to form an entry space for the hook to enter between the plate body and the inner cover by pressing the inner cover during assembly.

Abstract: The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes a gate stack, a hole penetrating the gate stack, and a channel structure. The hole has an undercut region defined on a sidewall thereof. The channel structure covers a portion of the undercut region and opens another portion of the undercut region.

Abstract: A semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked; first supports located in the gate structure, each first support including a second channel layer; second supports located in the gate structure, each second support including a barrier layer; and contact structures extending between the second supports through the gate structure, wherein each contact structure is connected to a corresponding conductive layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

Abstract: The present invention relates to a 6-(isooxazolidin-2-yl)-N-phenylpyrimidin-4-amine derivative, and a pharmaceutical composition for preventing or treating cancer comprising the compound as an effective component. The compound exhibits high inhibitory activity against an epidermal growth factor receptor (EGFR) variant, or wild-type or variants of one or more of ERBB2 and ERBB4, and thus may be usefully used in the treatment of cancers in which same are expressed. In particular, the compound exhibits excellent inhibitory activity on proliferation of lung cancer cell lines, and thus can be usefully used in the treatment of lung cancer.

Abstract: A semiconductor memory device includes a memory cell array, first to fourth I/O pads under the memory cell array and configured to connect with an external device, and first to fourth I/O driving modules between the memory cell array and the first to fourth I/O pads and configured to drive the first to fourth I/O pads, respectively. In a plan view, the first and second I/O driving modules are disposed symmetrically with respect to a first line extending in a first direction, the third and fourth I/O driving modules are disposed symmetrically with respect to the first line, the first and third I/O driving modules are disposed symmetrically with respect to a second line extending in a second direction crossing the first direction, and the second and fourth I/O driving modules are disposed symmetrically with respect to the second line.

Abstract: In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.

Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.

Abstract: A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.