Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region.

Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.

Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors.

Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.