Abstract: After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.

Abstract: A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

Abstract: A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets that satisfy at least one of the plurality of re-routing criteria. For each of the nets that satisfy at least one of the plurality of re-routing criteria: several operations are performed. The net is globally re-routed to determine a new global route for the net. Those of the nets that are within a given distance of the new global route are identified. The net is detail re-routed in accordance with the new global route without regard to those of the nets within the given distance of the new global route. Those of the nets within the given distance of the new global route are re-routed after completion of the detailed re-routing of the net.

Abstract: A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.

Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

Abstract: A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

Abstract: A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

Abstract: The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

Abstract: A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

Abstract: Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path.

Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

Abstract: The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

Abstract: A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.

Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

Abstract: A micro coaxial cable with a high bending performance, having an inner conductor; an insulating layer configured to surround the inner conductor, and a helical winding conductor configured to surround the insulating layer and having an elongation of 1.5 to 4% and a pitch of 3.0 to 5.0 mm.

Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

Abstract: A coaxial cable includes a central conductor made of cylindrical conductive material with conductivity greater than 100% and smaller than 104%, the central conductor having a thickness greater than 0.1 mm and smaller than 0.5 mm; a dielectric layer surrounding the central conductor and made of insulating material; an outer conductor surrounding the dielectric layer and made of conductive material with conductivity greater than 97% and smaller than 105% and a thickness greater than 0.24 mm and smaller than 0.35 mm; and an outer jacket surrounding the outer conductor. This coaxial cable allows stable transmission of signal even at a high frequency.

Abstract: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.