Patents by Inventor Gi-Joon Nam

Gi-Joon Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120110532
    Abstract: A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicant: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Gi-Joon Nam, David Anthony Papa, Chin Ngai Sze, Natarajan Viswanathan
  • Publication number: 20120054708
    Abstract: A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Alpert, John L. McCann, Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Natarajan Viswanathan
  • Patent number: 8108819
    Abstract: A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Gi-Joon Nam, Jarrod Alexander Roy, Natarajan Vishvanathan
  • Publication number: 20110302544
    Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy, Jarrod A. Roy, Taraneh Taghavi, Paul G. Villarrubia, Natarajan Viswanathan
  • Publication number: 20110302545
    Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Taraneh Taghavi, Gustavo E. Tellez, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 7934188
    Abstract: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Michael W. Dotson, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan
  • Publication number: 20110073348
    Abstract: A coaxial cable includes a central conductor made of cylindrical conductive material with conductivity greater than 100% and smaller than 104%, the central conductor having a thickness greater than 0.1 mm and smaller than 0.5 mm; a dielectric layer surrounding the central conductor and made of insulating material; an outer conductor surrounding the dielectric layer and made of conductive material with conductivity greater than 97% and smaller than 105% and a thickness greater than 0.24 mm and smaller than 0.35 mm; and an outer jacket surrounding the outer conductor. This coaxial cable allows stable transmission of signal even at a high frequency.
    Type: Application
    Filed: November 8, 2007
    Publication date: March 31, 2011
    Inventors: Chan-Yong Park, Bong-Kwon Cho, Gi-Joon Nam, Hyoung-Koog Lee, Jung-Won Park, Dae-Sung Lee
  • Patent number: 7897874
    Abstract: A foam coaxial cable includes a central conductor; an inner skin layer surrounding the central conductor coaxially; an insulation layer surrounding the inner skin layer coaxially and made of polyethylene resin containing a plurality of foam cells uniformly formed therein; wherein the inner skin layer is made of polyolefin resin having excellent compatibility with the polyethylene resin to increase an interfacial adhesive force with the insulation layer, an outer skin layer surrounding the insulation layer coaxially to prevent overfoaming of the insulation layer and allow uniform creation of foam cells; a shield surrounding the outer skin layer coaxially; and a jacket surrounding the shield. This cable improves an interfacial adhesive force between the central conductor and the insulation layer and also improves the degree of foam of the foam cells, thereby capable of propagating ultra high frequency of GHz level without signal interference.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: March 1, 2011
    Assignee: LS Cable Ltd.
    Inventors: Chan-Yong Park, Bong-Kwon Cho, Gi-Joon Nam, Jung-Won Park, Dae-Sung Lee
  • Patent number: 7882475
    Abstract: A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia, Natarajan Viswanathan
  • Publication number: 20100314152
    Abstract: The present invention relates to a micro coaxial cable with a high bending performance, comprising an inner conductor; an insulating layer configured to surround the inner conductor, and a helical winding conductor configured to surround the insulating layer and having an elongation of 1.5 to 4% and a pitch of 3.0 to 5.0 D.
    Type: Application
    Filed: November 8, 2007
    Publication date: December 16, 2010
    Inventors: Chan-Yong Park, ll-Gun Seo, Gi-Joon Nam, Jung-Won Park, In-Ha Kim, Gun-Joo Lee, June-Sun Kim
  • Publication number: 20100262944
    Abstract: A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Gi-Joon Nam, Jarrod Alexander Roy, Natarajan Vishvanathan
  • Publication number: 20100257498
    Abstract: Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 7, 2010
    Applicant: International Business Machines Corporation
    Inventors: Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Natarajan Viswanathan
  • Publication number: 20100230130
    Abstract: A foam coaxial cable includes a central conductor; an inner skin layer surrounding the central conductor coaxially; an insulation layer surrounding the inner skin layer coaxially and made of polyethylene resin containing a plurality of foam cells uniformly formed therein; wherein the inner skin layer is made of polyolefin resin having excellent compatibility with the polyethylene resin to increase an interfacial adhesive force with the insulation layer, an outer skin layer surrounding the insulation layer coaxially to prevent overfoaming of the insulation layer and allow uniform creation of foam cells; a shield surrounding the outer skin layer coaxially; and a jacket surrounding the shield. This cable improves an interfacial adhesive force between the central conductor and the insulation layer and also improves the degree of foam of the foam cells, thereby capable of propagating ultra high frequency of GHz level without signal interference.
    Type: Application
    Filed: August 10, 2007
    Publication date: September 16, 2010
    Applicant: LS CABLE LTD.
    Inventors: Chan-Yong Park, Bong-Kwon Cho, Gi-Joon Nam, Jung-Won Park, Dae-Sung Lee
  • Publication number: 20100192155
    Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: International Business Machines Corporation
    Inventors: Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia
  • Patent number: 7624366
    Abstract: The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: November 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, David J. Hathaway, William R. Migatz, Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia
  • Publication number: 20090271752
    Abstract: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Applicant: International Business Machines Corporation
    Inventors: Charles J. Alpert, Michael W. Dotson, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan
  • Patent number: 7541542
    Abstract: A micro coaxial cable includes an inner conductor; an insulation layer having foaming cells and formed to surround the inner conductor; an over-foaming preventing layer formed to surround the insulation layer for the purpose of uniform forming of the foaming cells; a metal shield layer formed to surround the over-foaming preventing layer; and a protective coating layer formed to surround the metal shield layer.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: June 2, 2009
    Assignee: LS Cable Ltd.
    Inventors: Chan-Yong Park, Gi-Joon Nam, Jung-Won Park, In-Ha Kim, June-Sun Kim, Il-Gun Seo, Gun-Joo Lee
  • Patent number: 7507910
    Abstract: A separator for a communication cable includes a plurality of barriers formed in a radial direction so that at least two pair units, in each of which at least two insulation-coated wires are spirally twisted, are received in spaces formed by the barriers one by one so as to separate the pair units from each other. At least one of the barriers has a relatively greater thickness than the other barriers. Thus, a communication cable having the separator may prevent PSNEXT (Power Sum Near and Crosstalk) caused by interference between adjacent wires when a high frequency signal is transmitted through the wires.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: March 24, 2009
    Assignee: LS Cable Ltd.
    Inventors: Chan-Yong Park, Jong-Seb Baeck, Gi-Joon Nam, Woo-Yong Dong
  • Patent number: 7467369
    Abstract: The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia
  • Publication number: 20080282213
    Abstract: A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
    Type: Application
    Filed: July 29, 2008
    Publication date: November 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Alpert, Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia, Natarajan Viswanathan