Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: A semiconductor system includes a slave and a master, wherein the slave includes a plurality of unit memory regions, and is configured to transmit determination result data generated by comparing reference data and test data, to the master, and wherein the master is configured to write the reference data and the test data in the plurality of unit memory regions.

Abstract: A buffer circuit includes a current mode circuit configured to generate output signals by converting a current path depending on input signals and configured to correct a swing width of the output signals by adjusting a current amount depending on a level of a compensation signal. The buffer circuit also includes a compensation signal generation circuit configured to detect a swing width variation of the output signals and configured to generate the compensation signal for correcting a swing width of the output signals to conform to a target value, depending on a detected swing width.

Abstract: A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.

Abstract: A buffer circuit includes a current mode circuit configured to generate output signals by converting a current path depending on input signals and configured to correct a swing width of the output signals by adjusting a current amount depending on a level of a compensation signal. The buffer circuit also includes a compensation signal generation circuit configured to detect a swing width variation of the output signals and configured to generate the compensation signal for correcting a swing width of the output signals to conform to a target value, depending on a detected swing width.

Abstract: A semiconductor system includes a slave and a master, wherein the slave includes a plurality of unit memory regions, and is configured to transmit determination result data generated by comparing reference data and test data, to the master, and wherein the master is configured to write the reference data and the test data in the plurality of unit memory regions.

Abstract: A semiconductor apparatus includes an input selection circuit that selects one of a first input signal and a second input signal in response to a control signal, and outputs the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different one another. The semiconductor apparatus also includes a conversion circuit that generates an output signal, in response to the selection signal, which swings to a level substantially identical to a level of the second input signal.

Abstract: A semiconductor apparatus includes an input selection circuit that selects one of a first input signal and a second input signal in response to a control signal, and outputs the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different one another. The semiconductor apparatus also includes a conversion circuit that generates an output signal, in response to the selection signal, which swings to a level substantially identical to a level of the second input signal.

Abstract: A semiconductor apparatus may include a command receiving circuit, a multiplexing circuit, and a DQ circuit. The command receiving circuit may be configured to latch signal bits of a command according to a clock signal, and output the latched signal bits as latched signals. The multiplexing circuit may be configured to receive the latched signals from the command receiving circuit, and selectively output the latched signals according to a flag signal which is internally generated within the semiconductor apparatus. The DQ circuit may be configured to receive the selectively outputted latched signals from the multiplexing circuit and receive the flag signal, and configured to output the selectively outputted latched signals and the flag signal as a feedback command to the outside of the semiconductor apparatus through a plurality of DQ pins.

Abstract: A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.

Abstract: A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.

Abstract: A semiconductor device includes: an inversion circuit suitable for inverting a first data clock in response to an inversion signal; a first phase detection unit suitable for comparing a phase of the first data clock transferred from the inversion circuit with a phase of a system clock and generating a first detection result; a second phase detection unit suitable for comparing a phase of a second data clock with the phase of the system clock and generating a second detection result; an inversion signal generation unit suitable for generating the inversion signal that is enabled when the first detection result and the second detection result are different from each other; a first transferring unit suitable for transferring the first detection result; and a second transferring unit suitable for transferring the second detection result.

Abstract: A data receiver includes a sampling clock generator configured to generate a sampling clock signal from an internal clock signal according to a data strobe signal, and a sampler configured to sample a data signal according to the sampling clock signal.

Abstract: An integrated circuit includes a ring oscillator including delay cells having a delay value and configured to generate two or more periodic waves, a first phase controller configured to compare the phase of a first selected periodic wave to the phase of a reference wave and change the delay value of the delay cells from a first delay value to a second delay value based on a first comparison signal corresponding to a phase difference between the first selected periodic wave and the reference wave, and a second phase controller configured to compare the phase of a second selected periodic wave to the phase of the reference wave and restore the delay value of the delay cells from the second delay value to the first delay value based on a second comparison signal corresponding to a phase difference between the second selected periodic wave and the reference wave.

Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.

Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.

Abstract: An integrated circuit includes a ring oscillator including delay cells having a delay value and configured to generate two or more periodic waves, a first phase controller configured to compare the phase of a first selected periodic wave to the phase of a reference wave and change the delay value of the delay cells from a first delay value to a second delay value based on a first comparison signal corresponding to a phase difference between the first selected periodic wave and the reference wave, and a second phase controller configured to compare the phase of a second selected periodic wave to the phase of the reference wave and restore the delay value of the delay cells from the second delay value to the first delay value based on a second comparison signal corresponding to a phase difference between the second selected periodic wave and the reference wave.