Patents by Inventor Gianluca Boselli
Gianluca Boselli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8306804Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.Type: GrantFiled: May 1, 2009Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, Jr.
-
Patent number: 8176460Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.Type: GrantFiled: May 1, 2009Date of Patent: May 8, 2012Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, Jr.
-
Publication number: 20110063765Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p?layer (38) includes functional circuitry (24) formed on the p?layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p? layer (38), a p?doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p? layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p?region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.Type: ApplicationFiled: November 22, 2010Publication date: March 17, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gianluca Boselli, Charvaka Duvvury
-
Patent number: 7838924Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.Type: GrantFiled: April 23, 2008Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Charvaka Duvvury
-
Publication number: 20100169845Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.Type: ApplicationFiled: May 1, 2009Publication date: July 1, 2010Applicant: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, JR.
-
Publication number: 20100169854Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.Type: ApplicationFiled: July 21, 2009Publication date: July 1, 2010Applicant: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, JR.
-
Publication number: 20100169064Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.Type: ApplicationFiled: May 1, 2009Publication date: July 1, 2010Applicant: Texas Instruments IncorporatedInventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, JR.
-
Patent number: 7728349Abstract: A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.Type: GrantFiled: October 11, 2005Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventor: Gianluca Boselli
-
Patent number: 7667243Abstract: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.Type: GrantFiled: April 25, 2007Date of Patent: February 23, 2010Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli
-
Publication number: 20090267154Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Applicant: Texas Instruments IncorporatedInventors: Gianluca Boselli, Charvaka Duvvury
-
Patent number: 7385383Abstract: Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ring oscillator and parametric degradation is measured to determine the effectiveness of the stress protection circuit in protecting the ring oscillator. A stress signal can be a voltage or current that stresses the normal operation of a functional circuit. The parametric degradation of the ring oscillator can be correlated to the parametric degradation that would be experienced by the functional circuit.Type: GrantFiled: June 3, 2005Date of Patent: June 10, 2008Assignee: Texas Instruments IncorporatedInventors: Vijay Kumar Reddy, Gianluca Boselli, Jeremy Charles Smith
-
Patent number: 7348643Abstract: A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.Type: GrantFiled: June 6, 2006Date of Patent: March 25, 2008Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Charvaka Duvvury
-
Publication number: 20070284666Abstract: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.Type: ApplicationFiled: April 25, 2007Publication date: December 13, 2007Applicant: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli
-
Publication number: 20070278581Abstract: A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.Type: ApplicationFiled: June 6, 2006Publication date: December 6, 2007Inventors: Gianluca Boselli, Charvaka Duvvury
-
Patent number: 7282767Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).Type: GrantFiled: June 17, 2005Date of Patent: October 16, 2007Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli, John E. Kunz, Jr.
-
Patent number: 7277263Abstract: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.Type: GrantFiled: September 8, 2004Date of Patent: October 2, 2007Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Gianluca Boselli
-
Patent number: 7256460Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.Type: GrantFiled: November 30, 2004Date of Patent: August 14, 2007Assignee: Texas Instruments IncorporatedInventors: Craig T. Salling, Charvaka Duvvury, Gianluca Boselli
-
Publication number: 20070090392Abstract: A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.Type: ApplicationFiled: October 11, 2005Publication date: April 26, 2007Inventor: Gianluca Boselli
-
Patent number: 7196887Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.Type: GrantFiled: May 28, 2003Date of Patent: March 27, 2007Assignee: Texas Instruments IncorporatedInventors: Gianluca Boselli, Vijay Kumar Reddy, Ekanayake Ajith Amerasekera
-
Publication number: 20060274473Abstract: Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ring oscillator and parametric degradation is measured to determine the effectiveness of the stress protection circuit in protecting the ring oscillator. A stress signal can be a voltage or current that stresses the normal operation of a functional circuit. The parametric degradation of the ring oscillator can be correlated to the parametric degradation that would be experienced by the functional circuit.Type: ApplicationFiled: June 3, 2005Publication date: December 7, 2006Inventors: Vijay Reddy, Gianluca Boselli, Jeremy Smith