Patents by Inventor Gil Bok CHOI
Gil Bok CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903200Abstract: A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.Type: GrantFiled: June 29, 2021Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Yu Jeong Lee, Dae Hwan Yun, Gil Bok Choi
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Publication number: 20240049469Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.Type: ApplicationFiled: October 16, 2023Publication date: February 8, 2024Applicant: SK hynix Inc.Inventors: Dae Hwan YUN, Gil Bok CHOI
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Patent number: 11894431Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.Type: GrantFiled: April 15, 2021Date of Patent: February 6, 2024Assignee: SK hynix Inc.Inventors: Dae Hwan Yun, Gil Bok Choi
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Patent number: 11882703Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.Type: GrantFiled: July 15, 2021Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventors: Sungmook Lim, Dae Hwan Yun, Gil Bok Choi, Jae Hyeon Shin, In Gon Yang, Hyung Jin Choi
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Patent number: 11812613Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.Type: GrantFiled: March 24, 2021Date of Patent: November 7, 2023Assignee: SK hynix Inc.Inventors: Dae Hwan Yun, Gil Bok Choi
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Patent number: 11790979Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.Type: GrantFiled: June 30, 2021Date of Patent: October 17, 2023Assignee: SK hynix Inc.Inventors: Gil Bok Choi, Dae Hwan Yun
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Publication number: 20230307073Abstract: A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.Type: ApplicationFiled: August 18, 2022Publication date: September 28, 2023Applicant: SK hynix Inc.Inventors: Gil Bok CHOI, Moon Sik SEO, Dae Hwan YUN
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Patent number: 11729981Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.Type: GrantFiled: March 29, 2022Date of Patent: August 15, 2023Assignee: SK hynix Inc.Inventors: Moon Sik Seo, Gil Bok Choi
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Patent number: 11521684Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.Type: GrantFiled: May 5, 2021Date of Patent: December 6, 2022Assignee: SK hynix Inc.Inventors: Gil Bok Choi, Dae Hwan Yun
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Publication number: 20220254805Abstract: A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.Type: ApplicationFiled: June 29, 2021Publication date: August 11, 2022Applicant: SK hynix Inc.Inventors: Yu Jeong LEE, Dae Hwan YUN, Gil Bok CHOI
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Publication number: 20220223620Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Moon Sik SEO, Gil Bok CHOI
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Publication number: 20220216231Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.Type: ApplicationFiled: July 15, 2021Publication date: July 7, 2022Applicant: SK hynix Inc.Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
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Publication number: 20220208246Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.Type: ApplicationFiled: June 30, 2021Publication date: June 30, 2022Applicant: SK hynix Inc.Inventors: Gil Bok CHOI, Dae Hwan YUN
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Publication number: 20220172780Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.Type: ApplicationFiled: May 5, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Gil Bok CHOI, Dae Hwan YUN
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Patent number: 11315944Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.Type: GrantFiled: October 23, 2019Date of Patent: April 26, 2022Assignee: SK hynix Inc.Inventors: Moon Sik Seo, Gil Bok Choi
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Publication number: 20220123113Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.Type: ApplicationFiled: April 15, 2021Publication date: April 21, 2022Applicant: SK hynix Inc.Inventors: Dae Hwan YUN, Gil Bok CHOI
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Publication number: 20220102371Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.Type: ApplicationFiled: March 24, 2021Publication date: March 31, 2022Applicant: SK hynix Inc.Inventors: Dae Hwan YUN, Gil Bok CHOI
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Publication number: 20220076754Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a first program operation and a second program operation on selected memory cells among the plurality of memory cells. The control logic may control the peripheral circuit to apply stepwise increasing and successive program pulses on the selected memory cells in a first program operation, and to apply program pulses and verify pulses on the selected memory cells in the second program operation.Type: ApplicationFiled: March 9, 2021Publication date: March 10, 2022Inventor: Gil Bok CHOI
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Publication number: 20210217456Abstract: A memory device, and a method of operating the memory device, includes: a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.Type: ApplicationFiled: July 7, 2020Publication date: July 15, 2021Applicant: SK hynix Inc.Inventors: Gil Bok CHOI, Moon Sik SEO
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Publication number: 20200395372Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.Type: ApplicationFiled: October 23, 2019Publication date: December 17, 2020Inventors: Moon Sik SEO, Gil Bok CHOI