Patents by Inventor Gil Bok CHOI

Gil Bok CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254805
    Abstract: A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.
    Type: Application
    Filed: June 29, 2021
    Publication date: August 11, 2022
    Applicant: SK hynix Inc.
    Inventors: Yu Jeong LEE, Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20220223620
    Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventors: Moon Sik SEO, Gil Bok CHOI
  • Publication number: 20220216231
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: July 7, 2022
    Applicant: SK hynix Inc.
    Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
  • Publication number: 20220208246
    Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.
    Type: Application
    Filed: June 30, 2021
    Publication date: June 30, 2022
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Dae Hwan YUN
  • Publication number: 20220172780
    Abstract: A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.
    Type: Application
    Filed: May 5, 2021
    Publication date: June 2, 2022
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Dae Hwan YUN
  • Patent number: 11315944
    Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Moon Sik Seo, Gil Bok Choi
  • Publication number: 20220123113
    Abstract: The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.
    Type: Application
    Filed: April 15, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20220102371
    Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.
    Type: Application
    Filed: March 24, 2021
    Publication date: March 31, 2022
    Applicant: SK hynix Inc.
    Inventors: Dae Hwan YUN, Gil Bok CHOI
  • Publication number: 20220076754
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a first program operation and a second program operation on selected memory cells among the plurality of memory cells. The control logic may control the peripheral circuit to apply stepwise increasing and successive program pulses on the selected memory cells in a first program operation, and to apply program pulses and verify pulses on the selected memory cells in the second program operation.
    Type: Application
    Filed: March 9, 2021
    Publication date: March 10, 2022
    Inventor: Gil Bok CHOI
  • Publication number: 20210217456
    Abstract: A memory device, and a method of operating the memory device, includes: a memory cell array including a plurality of strings; a voltage generation circuit configured to apply a turn-on voltage to the plurality of strings during a set application period in a channel initialization operation of a read operation of a selected string among the plurality of strings; a temperature detection circuit configured to measure an internal temperature of the memory device and generate a temperature signal; and control logic configured to control the voltage generation circuit to set the application period in response to the temperature signal and apply the turn-on voltage to the plurality of strings during the set application period.
    Type: Application
    Filed: July 7, 2020
    Publication date: July 15, 2021
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Moon Sik SEO
  • Publication number: 20200395372
    Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
    Type: Application
    Filed: October 23, 2019
    Publication date: December 17, 2020
    Inventors: Moon Sik SEO, Gil Bok CHOI
  • Patent number: 10394652
    Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
  • Patent number: 10353776
    Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
  • Patent number: 10296226
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
  • Patent number: 10224102
    Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Gil Bok Choi, Sung Hoon Cho, Sung Ho Kim, Min Sang Park, Kyong Taek Lee, Myoung Kwan Cho
  • Publication number: 20190065059
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Application
    Filed: October 31, 2018
    Publication date: February 28, 2019
    Applicant: SK hynix Inc.
    Inventors: Sung Ho KIM, Min Sang PARK, Yong Seok SUH, Kyong Taek LEE, Gil Bok CHOI
  • Patent number: 10146442
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 4, 2018
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
  • Publication number: 20180336949
    Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.
    Type: Application
    Filed: December 8, 2017
    Publication date: November 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Gil Bok CHOI, Sung Hoon CHO, Sung Ho KIM, Min Sang PARK, Kyong Taek LEE, Myoung Kwan CHO
  • Publication number: 20180188958
    Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
    Type: Application
    Filed: July 6, 2017
    Publication date: July 5, 2018
    Applicant: SK hynix Inc.
    Inventors: Sung Ho KIM, Min Sang PARK, Yong Seok SUH, Kyong Taek LEE, Gil Bok CHOI
  • Patent number: 9977712
    Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min Sang Park, Suk Kwang Park, Yun Bong Lee, Sung Hoon Cho, Gil Bok Choi