Patents by Inventor Gil Bok CHOI
Gil Bok CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10394652Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.Type: GrantFiled: November 2, 2015Date of Patent: August 27, 2019Assignee: SK hynix Inc.Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
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Patent number: 10353776Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.Type: GrantFiled: November 2, 2015Date of Patent: July 16, 2019Assignee: SK hynix Inc.Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
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Patent number: 10296226Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.Type: GrantFiled: October 31, 2018Date of Patent: May 21, 2019Assignee: SK hynix Inc.Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
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Patent number: 10224102Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.Type: GrantFiled: December 8, 2017Date of Patent: March 5, 2019Assignee: SK hynix Inc.Inventors: Gil Bok Choi, Sung Hoon Cho, Sung Ho Kim, Min Sang Park, Kyong Taek Lee, Myoung Kwan Cho
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Publication number: 20190065059Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.Type: ApplicationFiled: October 31, 2018Publication date: February 28, 2019Applicant: SK hynix Inc.Inventors: Sung Ho KIM, Min Sang PARK, Yong Seok SUH, Kyong Taek LEE, Gil Bok CHOI
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Patent number: 10146442Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.Type: GrantFiled: July 6, 2017Date of Patent: December 4, 2018Assignee: SK hynix Inc.Inventors: Sung Ho Kim, Min Sang Park, Yong Seok Suh, Kyong Taek Lee, Gil Bok Choi
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Publication number: 20180336949Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.Type: ApplicationFiled: December 8, 2017Publication date: November 22, 2018Applicant: SK hynix Inc.Inventors: Gil Bok CHOI, Sung Hoon CHO, Sung Ho KIM, Min Sang PARK, Kyong Taek LEE, Myoung Kwan CHO
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Publication number: 20180188958Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.Type: ApplicationFiled: July 6, 2017Publication date: July 5, 2018Applicant: SK hynix Inc.Inventors: Sung Ho KIM, Min Sang PARK, Yong Seok SUH, Kyong Taek LEE, Gil Bok CHOI
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Patent number: 9977712Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.Type: GrantFiled: December 11, 2015Date of Patent: May 22, 2018Assignee: SK Hynix Inc.Inventors: Min Sang Park, Suk Kwang Park, Yun Bong Lee, Sung Hoon Cho, Gil Bok Choi
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Patent number: 9859014Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.Type: GrantFiled: July 18, 2016Date of Patent: January 2, 2018Assignee: SK hynix Inc.Inventors: Min Sang Park, Sung Ho Kim, Kyong Taek Lee, Yun Bong Lee, Gil Bok Choi
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Publication number: 20170229189Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.Type: ApplicationFiled: July 18, 2016Publication date: August 10, 2017Inventors: Min Sang PARK, Sung Ho KIM, Kyong Taek LEE, Yun Bong LEE, Gil Bok CHOI
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Publication number: 20170011801Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.Type: ApplicationFiled: September 23, 2016Publication date: January 12, 2017Inventors: Min Sang PARK, Yun Bong LEE, Suk Kwang PARK, Hwang HUH, Dong Wook LEE, Myung Su KIM, Sung Hoon CHO, Sang Jo LEE, Chang Jin SUNWOO, Gil Bok CHOI
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Publication number: 20170004037Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.Type: ApplicationFiled: December 11, 2015Publication date: January 5, 2017Inventors: Min Sang PARK, Suk Kwang PARK, Yun Bong LEE, Sung Hoon CHO, Gil Bok CHOI
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Publication number: 20160357472Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.Type: ApplicationFiled: November 2, 2015Publication date: December 8, 2016Inventors: Gil Bok CHOI, Suk Kwang PARK, Min Sang PARK
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Patent number: 9478304Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.Type: GrantFiled: January 8, 2015Date of Patent: October 25, 2016Assignee: SK Hynix Inc.Inventors: Min Sang Park, Yun Bong Lee, Suk Kwang Park, Hwang Huh, Dong Wook Lee, Myung Su Kim, Sung Hoon Cho, Sang Jo Lee, Chang Jin Sunwoo, Gil Bok Choi
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Publication number: 20160049200Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.Type: ApplicationFiled: January 8, 2015Publication date: February 18, 2016Inventors: Min Sang PARK, Yun Bong LEE, Suk Kwang PARK, Hwang HUH, Dong Wook LEE, Myung Su KIM, Sung Hoon CHO, Sang Jo LEE, Chang Jin SUNWOO, Gil Bok CHOI