Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

Abstract: Disclosed is a device and method for controlling driving operations of a vehicle in a coasting situation. The device may include a vehicle speed detector, a coasting drivable range operator, and a controller. The vehicle speed detector detects a current vehicle speed when signals from an accelerator position sensor and a brake pedal position sensor are both zero (0). The coasting drivable range operator determines whether or not coasting is possible by receiving a current location of the vehicle, road conditions and location information, and information related to an inter-vehicle distance when the current vehicle speed is equal to or greater than a certain speed. The controller turns off a motor in response to determining that the coating is possible when an inter-vehicle distance between the vehicle and a preceding vehicle is equal to or greater than a predetermined distance.

Abstract: Piperidine compounds and pharmaceutically useful salts thereof, a pharmaceutical composition including an effective amount of the racemic or enantiomerically enriched piperidine compounds to treat gastrointestinal diseases, and a method of treating gastrointestinal diseases in a mammal are provided.

Abstract: An apparatus for manufacturing molten iron includes a reduction furnace having a charging device that is capable of preventing segregation. The reduction furnace for reducing an iron-containing material used for manufacturing molten iron may include a charging hole where the iron-containing material is charged, a first guide plate sloped toward a first direction in the reduction furnace to guide the iron-containing material to the inside of the reduction furnace, and a second guide plate fixed and sloped toward a second direction intersecting the first direction in the reduction furnace to guide the iron-containing material dropped and guided by the first guide plate. A dropping direction of the iron-containing material dropped and guided by the first guide plate is changed when the iron-containing material is guided by the second guide plate.

Abstract: The present invention discloses a reserve battery having an all solid state thin film battery (5). The reserve battery includes: a housing (1) made of a conductive material; an insulation coating (2) formed on the inner surface of the housing (1); an all solid state thin film battery formed in the housing; a switching System (3) disposed between the housing (1) and the all solid state thin film battery; and an external (6) terminal electrically connected to the all solid state thin film battery, for externally providing electrical connection through the opened surface of the housing. The reserve battery overcomes disadvantages of a general reserve battery using an electrolyte solution.

Abstract: A semiconductor memory includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line in response to a column select signal; and a read circuit configured to precharge the selected bit line in response to a precharge signal, to apply a read bias to the precharged bit line in response to a read bias provision signal, and to read data from the memory cells. A resistance level of each of the memory cells varies according to data stored therein, and the read circuit reads data from a first memory cell of the plurality of memory cells in response to the precharge signal having a first pulse width and reads data from a second memory cell of the plurality of memory cells in response to the precharge signal having a second pulse width.

Abstract: A method for registering a Smartphone when accessing security authentication device and a method for access authentication of a registered Smartphone are provided. When a Smartphone based application searches for a device and attempts an access to the found device, the search and access for the device is limited according to a result of authentication using an activation code.

Abstract: A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.

Abstract: In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.

Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

Abstract: A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.

Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.

Abstract: A nonvolatile memory device includes a memory cell array with a matrix of nonvolatile memory cells. The nonvolatile memory cells may store data using variable resistive elements. A plurality of bitlines are coupled to a plurality of nonvolatile memory cell arrays in the memory cell array. A column selection circuit selects among the bitlines in response to a column selection signal. A controller regulates a level of the column selection signal in response to a temperature signal from a temperature sensor. The temperature sensor may be configured to measure temperature outside the nonvolatile memory device to generate the temperature signal.

Abstract: Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

Abstract: The present invention relates to a sensor comprising a resorufin compound having sulfite ion selectivity and a method for detecting sulfite ions using the same. More specifically, the resorufin compound may have outstandingly increased fluorescence intensity by a deprotection reaction that a levulinyl group is cleaved with a sulfite ion to be used as a selective fluorescence sensor of turn-on type, and also represent a chromogenic change to detect sulfite ions by naked eye.

Abstract: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.

Abstract: The invention provides a heat treatment apparatus, in which an intake valve (91a) is mounted on an ambient gas feed pipe (91) connected to a heating chamber (12), an exhaust valve (131a) is mounted on an exhaust pipe (131), and a pressure sensor (150) is provided on the heating chamber (12). Through the control of a control unit (80) connected to the pressure sensor (150), to the intake valve (91a) and to the exhaust valve (131a), the intake valve (91a) and the exhaust valve (131a) are opened or closed, thus supplying ambient gas into the heating chamber (12) or exhausting ambient gas from the cooling chamber (13) depending on an internal pressure of the heating chamber (12). Thus, the amount of ambient gas used in heat treating workpieces (1) is minimized and thus operational costs are reduced. It is possible to prevent accidents such as gas explosions as well as to reduce environmental contamination caused by the combustion of ambient gas.

Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: This invention relates to a composition for producing a cathode for an electricity storage device, including carbon nanofibers prepared by electrospinning a spinning solution including a cathode active material, a conductive material and a carbon fiber precursor; and a binder, and to a cathode for an electricity storage device made with the composition and to an electricity storage device including the cathode. The composition for producing a cathode includes carbon nanofibers instead of part or all of a conductive material, a dispersant and/or a binder, so that the cathode has remarkably increased specific surface area and electrical conductivity (decreased resistance), thus maximizing the efficiency of the cathode active material and the capacity.