Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile memory cells, write global bit lines shared by the plurality of memory banks, read global bit lines shared by the plurality of memory banks, and a dummy global bit line arranged between the write global bit lines and the read global bit lines, wherein the dummy global bit line is configured and operable to reduce noise affecting a write bit line involved in a write operation or noise affecting a read global bit line involved in a read operation.

Abstract: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively. A read circuit reads resistance levels of the first and second nonvolatile memory cells by providing first and second read bias currents of different levels to the first and second bit lines, respectively.

Abstract: A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.

Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

Abstract: A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.

Abstract: A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell, and a read circuit which provides the multi level memory cell with a read bias and performs a sensing operation in response to the read bias, wherein the read bias has at least two levels during a read cycle.

Abstract: A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance memory cells and the bit lines to receive a first control voltage being applied to their gates, includes making the first control voltage at a first level, and changing a resistance of the variable resistance memory cells by providing a write bias to the variable resistance cells; verifying and reading whether the changed resistance enters into a specified resistance window; and changing the first control voltage to a second level that is different from the first level, and changing the resistance of the variable resistance memory cells by providing the write bias to the variable resistance memory cells.

Abstract: Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material.

Abstract: A multilevel nonvolatile memory device using a resistance material is provided. The multilevel nonvolatile memory device includes at least one multilevel memory cell and a read circuit. The at least one multilevel memory cell has a level of resistance that varies according to data stored therein. The read circuit first reads first bit data from the multilevel memory cell by providing a first read bias to the multilevel memory cell and secondarily reads second bit data from the multilevel memory cell by providing a second read bias to the multilevel memory cell. The second read bias varies according to a result of the first reading.

Abstract: A method of controlling the voltage of a sub-wordline in a variable resistive memory device includes switchably passing a voltage from a main wordline to the sub-wordline, and substantially blocking forward current flow from the sub-wordline to a variable resistive memory cell of the device.

Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

Abstract: The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

Abstract: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.

Abstract: Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; and a line selecting unit simultaneously selecting word lines of the plurality of memory blocks and simultaneously selecting bit lines of the memory blocks belonging to the same memory sector among the plurality of memory blocks in an access operation mode.

Abstract: A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of the memory cells in a second sector, local bitlines where each is in signal communication a memory cell, a local bitline selecting signal generator in signal communication with local bitline selecting signal paths, a first local bitline selecting signal path in signal communication with a first pair of the local bitlines, and a second local bitline selecting signal path in signal communication with a second pair of the plurality of local bitlines, where a first of the first pair of local bitlines is in signal communication with a first of the first pair of the memory cells in the first sector and a second of the first pair of local bitlines is in signal communication with a second of the second pair of the memory cells in

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

Abstract: A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines.

Abstract: A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.

Abstract: The present invention relates to a novel piperazine derivative or pharmaceutically acceptable salt thereof, a process for preparing the same, a pharmaceutical composition for treating central nervous system diseases comprising an effective amount of the piperazine compound and a method of treating central nervous system (CNS) disorder such as psychosis in a mammal.

Abstract: A mercury selective fluorescent chemosensor for detecting mercury ions by a compound represented by formula 1 and a novel fluorescent sensitive compound prepared by introducing two aminopyrene functions as a fluorescent sensitive moiety into a binding site of the compound of formula 1 is used for selectively detecting mercury ions are provided. The mercury selective fluorescent sensitive chemosensor is a switch type chemosensor having ON-OFF-type Hg2+-selective fluorescence quenching behavior and is not affected by other coexistent metal ions. Changes in fluorescence of the compounds of formula 1 were analyzed by ratiometric approach using monomer and excimer emissions of the pyrene fluorophore to selectively signal the concentration of mercury ions. The chemosensor can detect mercury ions in a micromolar unit even in a solution including an excess of water. Accordingly, the mercury selective fluorescent chemosensor for detecting mercury ions can be used effectively in environmental and medical applications.