Abstract: The present invention includes an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. In embodiments, the active pixel sensor can be implemented in a standard CMOS process, without the need for a specialized optical process. The active pixel sensor includes a reset FET, a photo-diode, a source follower, and a current source. The photo-diode is coupled to the source of the reset FET at a discharge node. The drain of the reset FET is couple to a power supply VDD. The discharge node is also coupled to the gate input of the source follower, the output of which is coupled to output node. In embodiments, shallow trench isolation is inserted between the active devices that constitute the photo-diode, the source follower, or the current source, where the shallow trench isolation reduces leakage current between these devices. As a result, dark current is reduced and overall sensitivity is improved.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software modes, is used with the plurality of memory cells to indicate that at least one memory cells is unusable and should be shifted out of operation. The software mode comprises a software programmable element adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware mode comprises a hardware element adapted to indicate the at least one memory cell is unusable and is gated with the software programmable element.

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices.

Abstract: Aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a BIST module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test. An identity of the loaded instruction may be determined subsequent to loading the instruction into the parameterized shift register. A plurality of test signals may be generated which correspond to the determined identity of the loaded instruction. In this regard, each of the generated plurality of test signals may control the execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules that make up the embedded device under test.

Abstract: Aspects of the invention may include a software programmable verification tool for testing and debugging an embedded device under test by generating an instruction for causing at least one predetermined test to be executed by a BIST module on the embedded device under test. The generated instruction may be loaded into a parameterized shift register of the BIST module. An identity of at least one predetermined test may be determined based on the loaded instruction. At least one signal corresponding to the determined identity of the at least one predetermined test may be generated for causing control and execution of the testing and debugging of the device under test.

Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.

Abstract: An electron beam apparatus is capable of registering an image on a substrate. The apparatus comprises a vacuum chamber having a wall. Electron beam source, modulator, and detector components are adapted to generate, modulate and detect an array of electron beams in the vacuum chamber. A circuit board passing through the wall of the vacuum chamber has a plurality of electrical traces to connect to the electron beam source, modulator, and detector components.

Abstract: An electron beam apparatus is capable of registering an image on a substrate. The apparatus comprises a vacuum chamber having a wall. Electron beam source, modulator, and detector components are adapted to generate, modulate and detect an array of electron beams in the vacuum chamber. A circuit board passing through the wall of the vacuum chamber has a plurality of electrical traces to connect to the electron beam source, modulator, and detector components.