Abstract: An ice-lined vaccine refrigerator includes a vaccine storage compartment, an electrically powered cooling circuit, the electrically powered cooling circuit being configured to generate an ice-lining and to cool the vaccine storage compartment; an AC power inlet adapted for connection to an external supply of AC power; and a refrigerant compressor forming part of the electrically powered cooling circuit and adapted to be powered by the external supply of AC power through the AC power inlet. Reliability is improved by using a DC powered compressor and an AC/DC convertor to convert AC power received at the AC power inlet to DC power to power the compressor.

Abstract: A cold storage device, notably a freezer configured to operate at a temperature which is ??30° C., includes a door seal which comprises a single piece door seal, the single piece door seal comprising i) a sealing portion configured to provide a seal between the door and the door frame when the door is in its closed position and ii) a thermal insulating portion which, when the door is in its closed position, extends at least partially between inner periphery of the door frame and the outer periphery of the door frame.

Abstract: An ice-lined cold storage device (10) comprising: a cold storage compartment (15) arranged at an interior of the ice-lined cold storage device; an ice-lining (25a, 25b, 25c, 25d) configured to absorb heat from the interior of the cold-storage device; a cooling circuit (16) configured, when in operation, to remove heat from the ice-lining; an inner liner (22) arranged between the cold storage compartment and the ice-lining, the inner liner comprising a sheet material (23) having a major surface which faces towards the cold storage compartment and a major surface (27) which faces towards the ice-lining; is provided with an electrical heating element (26) arranged at one of the said major surfaces of the inner to provide heat to the interior of the cold storage device.

Abstract: A cold storage device, notably a freezer configured to operate at a temperature which is ??30° C., includes a door seal which comprises a single piece door seal, the single piece door seal comprising i) a sealing portion configured to provide a seal between the door and the door frame when the door is in its closed position and ii) a thermal insulating portion which, when the door is in its closed position, extends at least partially between inner periphery of the door frame and the outer periphery of the door frame.

Abstract: An ice-lined vaccine refrigerator includes a vaccine storage compartment, an electrically powered cooling circuit, the electrically powered cooling circuit being configured to generate an ice-lining and to cool the vaccine storage compartment; an AC power inlet adapted for connection to an external supply of AC power; and a refrigerant compressor forming part of the electrically powered cooling circuit and adapted to be powered by the external supply of AC power through the AC power inlet. Reliability is improved by using a DC powered compressor and an AC/DC convertor to convert AC power received at the AC power inlet to DC power to power the compressor.

Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.

Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

Abstract: A method for composing a multilayer video image of which the values of the pixels of the image layers are stored in a memory. The video image may include at least one first image layer and a second image layer located in front of the at least one first layer and having an opaque area. The method may include defining a region of the at least one first image layer to be hidden by the opaque area, reading from the memory the stored pixel values, with the exception of the values of the pixels of the region of the at least one first image layer, and composing the video image at least from the read pixel values.

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.

Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.

Abstract: A conversion between two texture compression formats comprises calculations performed at index-level for reducing handling of values with color bit-length and an amount of calculations with color values. Format conversion can thus be performed in real time upon displaying an image using the compressed texture data, without significant slowing down of a display rate of the images. It may be implemented in particular for conversion from DXT1—to ETC1 compression format, and a non-flipped or flipped orientation of an ETC1—compressed texture data block can thus be determined from said texture data block as initially compressed in DXT1 format.

Abstract: It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; determining whether the monitored value reaches a trigger value; when the monitored value reaches the trigger value (S120): modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; when the monitored value reaches a second time the trigger value (S170): modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract: A method for storing data in storage blocks having a constant storage size may include grouping the data into successive data groups, and compressing each data group into a compressed block having a block size smaller than or equal to the storage size. The method may further include, for at least one compressed block having a block size smaller than the storage size, inserting into the at least one compressed block, before storage in a storage block, at least one information element relating to the contents of at least one further compressed block.

Abstract: A method for composing a multilayer video image of which the values of the pixels of the image layers are stored in a memory. The video image may include at least one first image layer and a second image layer located in front of the at least one first layer and having an opaque area. The method may include defining a region of the at least one first image layer to be hidden by the opaque area, reading from the memory the stored pixel values, with the exception of the values of the pixels of the region of the at least one first image layer, and composing the video image at least from the read pixel values.

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.

Abstract: This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of a group of bits is found (S14), the most probable first bit being checked first, wherein the checks are iterated in a checking order of bits different from a chronological reception order, so as to check earlier at least one of most probable first bits, different from the most probable first bit, so as to shorten average resynchronization time.

Abstract: A method generates an image from a set of image zones each delimited by a contour of polygonal shape defined by a set of vertexes, and comprising pixels having an attribute value which can be deduced from the value of a corresponding attribute of each of the vertexes of the image zone. The method includes determining to within a pixel the pixels that belong to each image zone according to the dimensions in number of pixels of the image to be generated; associating the pixels of each image zone in blocks of pixels; and determining an attribute value for each block of pixels of each image zone as a function of the value of the corresponding attribute of each vertex of the image zone.