Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract: This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of a group of bits is found (S14), the most probable first bit being checked first, wherein the checks are iterated in a checking order of bits different from a chronological reception order, so as to check earlier at least one of most probable first bits, different from the most probable first bit, so as to shorten average resynchronization time.

Abstract: A conversion between two texture compression formats comprises calculations performed at index-level for reducing handling of values with color bit-length and an amount of calculations with color values. Format conversion can thus be performed in real time upon displaying an image using the compressed texture data, without significant slowing down of a display rate of the images. It may be implemented in particular for conversion from DXT1—to ETC1 compression format, and a non-flipped or flipped orientation of an ETC1—compressed texture data block can thus be determined from said texture data block as initially compressed in DXT1 format.

Abstract: It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; determining whether the monitored value reaches a trigger value; when the monitored value reaches the trigger value (S120): modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; when the monitored value reaches a second time the trigger value (S170): modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.

Abstract: A video transmission circuit for transmitting video data on a digital serial interface to a receive circuit arranged to process the video data at a constant rate, the circuit including a transmission block comprising: a packet generator arranged to generate, for each image of the video data, a plurality of packets, each containing a pixel group of the image; a transmit circuit arranged to transmit the packets of each image on a digital serial interface at time intervals based on the constant rate; and a synchronization circuit arranged to receive from the receive circuit, after transmission of a plurality of packets, a synchronization signal for synchronizing the beginning of the transmission of a next packet.

Abstract: A method of compressing at least a part of a digital image comprises the steps of: dividing said digital image into groups of pixels; assigning a first information to each group of pixels wherein said first information indicates at least two reference colors selected for said group of pixels and, for each pixel in said group of pixels, which reference color or combination thereof is selected; assigning a second information to each group of pixels indicating a mode of compression used for said group of pixels; said first information indicating at least a third color for at least one of said groups of pixels.

Abstract: A method generates an image from a set of image zones each delimited by a contour of polygonal shape defined by a set of vertexes, and comprising pixels having an attribute value which can be deduced from the value of a corresponding attribute of each of the vertexes of the image zone. The method includes determining to within a pixel the pixels that belong to each image zone according to the dimensions in number of pixels of the image to be generated; associating the pixels of each image zone in blocks of pixels; and determining an attribute value for each block of pixels of each image zone as a function of the value of the corresponding attribute of each vertex of the image zone.

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.

Abstract: A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the data input and applies the processed data at the data output. The processor may further generate a block request. A control device within the module reproduces, at the block output, a block request applied to the block input or generated by the processing component. The control device thus may operate to block the application of processed data at the data output upon receipt of a block request at the block input. Two or more dedicated processing modules may be connected in series with each other to form a processing flow chain with the data output of one module connected to the data input of a subsequent module. Additionally, the block output of the subsequent module is connected to the block input of the preceding module.

Abstract: A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the data input and applies the processed data at the data output. The processor may further generate a block request. A control device within the module reproduces, at the block output, a block request applied to the block input or generated by the processing component. The control device thus may operate to block the application of processed data at the data output upon receipt of a block request at the block input. Two or more dedicated processing modules may be connected in series with each other to form a processing flow chain with the data output of one module connected to the data input of a subsequent module. Additionally, the block output of the subsequent module is connected to the block input of the preceding module.

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.