Patents by Inventor Gin Yee
Gin Yee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220343934Abstract: The technology disclosed herein enables compensation for attenuation caused by face coverings in captured audio. In a particular embodiment, a method includes determining that a face covering is positioned to cover the mouth of a user of a user system. The method further includes receiving audio that includes speech from the user and adjusting amplitudes of frequencies in the audio to compensate for the face covering.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Inventors: John C. Lynch, Miguel De Araujo, Gurbinder Singh Kalkat, Eugene Pung-Gin Yee, Christopher Bruce McArthur
-
Patent number: 11023403Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: GrantFiled: December 2, 2019Date of Patent: June 1, 2021Assignee: Apple Inc.Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
-
Publication number: 20200183874Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: ApplicationFiled: December 2, 2019Publication date: June 11, 2020Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
-
Patent number: 10521391Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.Type: GrantFiled: November 29, 2018Date of Patent: December 31, 2019Assignee: Apple Inc.Inventors: Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Brian S. Leibowitz, Pradeep R. Trivedi, Gin Yee, Emerson S. Fang
-
Patent number: 9838025Abstract: An apparatus includes circuitry and an oscillator circuit that may be configured to generate a clock signal dependent upon a control signal. The circuitry may be configured to perform a frequency measurement of the clock signal. In response to a determination that the frequency of the clock signal is greater than a first threshold, the circuitry may also be configured to perform a phase comparison between a divided clock signal and a reference clock signal, and to adjust a value of the control signal such that the adjusted value depends upon a result of the comparison. In response to a determination that the frequency of the clock signal is less than the first threshold, the circuitry may be configured to adjust the value of the control signal such that the adjusted value depends upon a result of the measurement.Type: GrantFiled: August 10, 2016Date of Patent: December 5, 2017Assignee: Apple Inc.Inventors: Wei Deng, Dennis Fischette, Jr., Gin Yee
-
Patent number: 7688925Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.Type: GrantFiled: August 1, 2005Date of Patent: March 30, 2010Assignee: ATI Technologies, Inc.Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji Menokki Kandiyil, Gin Yee, Joseph Macri
-
Patent number: 7519739Abstract: In a server system coupled to at least one client system, a method for synchronizing a user interface (UI) presentation to be displayed to a user of the client system to a UI description maintained by the server system, the method comprising the steps of: converting the UI description into one or more UI object definitions; storing each UI object definition in a document; and, transmitting the document to the client system; the client system adapted to convert the UI object definitions to UI objects to generate the UI presentation.Type: GrantFiled: August 11, 2004Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: John W. Comeau, Gin Yee Ng, Victor Ka Chun Yu
-
Publication number: 20080281911Abstract: A system coupled to at least one client system, a system for synchronizing a user interface (UI) presentation to be displayed to a user of the client system to a UI description maintained by the server system, the server system comprising a UI object converter adapted for converting the UI description into one or more UI object definitions; storing each UI object definition in a document; and, transmitting the document to the client system; the client system adapted to convert the UI object definitions to UI objects to generate the UI presentation.Type: ApplicationFiled: July 23, 2008Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John W. COMEAU, Gin Yee Ng, Victor Ka Chun Yu
-
Publication number: 20070036020Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.Type: ApplicationFiled: August 1, 2005Publication date: February 15, 2007Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji M.K., Gin Yee, Joseph Macri
-
Patent number: 6976235Abstract: A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.Type: GrantFiled: September 18, 2002Date of Patent: December 13, 2005Assignee: Sun Microsystems, Inc.Inventors: Sudhakar Bobba, Gin Yee, Pradeep Trivedi
-
Patent number: 6971079Abstract: A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.Type: GrantFiled: September 18, 2002Date of Patent: November 29, 2005Assignee: Sun Microsystems, Inc.Inventors: Gin Yee, Pradeep Trivedi, Sudhakar Bobba
-
Publication number: 20050168255Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.Type: ApplicationFiled: February 4, 2004Publication date: August 4, 2005Inventors: Claude Gauthier, Pradeep Trivedi, Raymond Heald, Gin Yee
-
Publication number: 20050114061Abstract: A temperature monitoring technique that eliminates the need for bipolar devices. In one embodiment of the present invention, a long-channel MOS transistor is configured in a diode connection to sense change in temperature. The diode drives a linear regulator and an oscillator. The oscillator in turn drives a counter, which counts pulses for a fixed period of time. The system clock on the chip is used as a temperature-independent frequency to generate a count. The temperature-dependent frequency is counted for a fixed number of system clock cycles. The present invention eliminates band gap circuitry currently used in most thermal sensing devices to provide a temperature-independent reference.Type: ApplicationFiled: November 10, 2003Publication date: May 26, 2005Inventors: Claude Gauthier, Gin Yee
-
Patent number: 6882196Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.Type: GrantFiled: July 18, 2002Date of Patent: April 19, 2005Assignee: Sun Microsystems, Inc.Inventors: Gin Yee, Sudhakar Bobba, Claude Gauthier, Dean Liu, Lynn Ooi, Pradeep Trivedi
-
Publication number: 20040054979Abstract: A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.Type: ApplicationFiled: September 18, 2002Publication date: March 18, 2004Inventors: Sudhakar Bobba, Gin Yee, Pradeep Trivedi
-
Publication number: 20040054975Abstract: A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.Type: ApplicationFiled: September 18, 2002Publication date: March 18, 2004Inventors: Gin Yee, Pradeep Trivedi, Sudhakar Bobba
-
Patent number: 6707320Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.Type: GrantFiled: November 30, 2001Date of Patent: March 16, 2004Assignee: Sun Microsystems, Inc.Inventors: Pradeep Trivedi, Gin Yee
-
Publication number: 20040012428Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.Type: ApplicationFiled: July 18, 2002Publication date: January 22, 2004Inventors: Gin Yee, Sudhakar Bobba, Claude Gauthier, Dean Liu, Lynn Ooi, Pradeep Trivedi
-
Patent number: 6642756Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.Type: GrantFiled: July 25, 2002Date of Patent: November 4, 2003Assignee: Sun Microsystems, Inc.Inventors: Gin Yee, Sudhakar Bobba, Lynn Ooi, Pradeep Trivedi
-
Publication number: 20030163750Abstract: A clock grid skew reduction technique that uses one or more biasable delay drivers to compensate for unbalanced loading and/or RC wire delay induced skew is provided. The biasable delay driver has a size that may be varied depending on a delay amount of a signal from a clock source to an input of the biasable delay driver. Depending on the delay amount, the biasable delay driver may be either sized up or sized down to modulate delay in order to reduce or eliminate skew between the clock signal at the input of the biasable delay driver and the clock signal at another point in a circuit.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Inventors: Pradeep Trivedi, Lynn Ooi, Gin Yee