Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: An integrated circuit having a clock driver connected to a non-peripheral region of a clock grid is provided. Providing interconnect that connect a clock driver to non-peripheral regions the clock grid effectively leads to reduced clock skew due to reduced RC delays from clock grid connection points to components operatively connected to the clock grid. Further, a method for reducing clock skew on a clock grid using a wire tree architecture structure is provided.

Abstract: A lock detect indicator capable of dynamically determining whether a phase locked loop is in lock or out of lock is provided. The lock detect indicator uses pulses on the fast and slow signals generated by a phase-frequency detector of the phase locked loop to determine if the phase locked loop has been continuously trying to speed up or slow down itself for a predefined amount of time, in which case, the lock detect indicator indicates that the phase locked loop is out of lock. Further, a lock detect indicator capable of indicating whether a phase locked loop previously went out of lock is provided. Further, a method for detecting whether a phase locked loop is out of lock or in lock is provided.

Abstract: A method for improving the speed of conventional CMOS logic families is disclosed. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4× to 5× over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

Abstract: A system for remotely debugging application code on client/server systems. The system comprises a kicker program and a debugging engine installed on the server and a debugging user interface installed on a client machine. When a call is made to the application code on the server machine, the kicker program starts the debugging engine to debug the application code. The kicker program stops the debugging engine when the application code has been stepped through or returns. The debugging engine includes means for remotely starting the debugging user interface installed on the client machine.