Patents by Inventor Giovanni De Micheli
Giovanni De Micheli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10394988Abstract: A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ?. The method further comprises providing a commutativity, a majority (?.M), an associativity (?.A), a distributivity (?.D), an inverter propagation (?.I), a relevance (?.R), a complementary associativity (?.C), and a substitution (?.S) transformation; and combining the ?.M, ?.C, ?.A, ?.D, ?.I, ?.R, ?.C and ?.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the ?.A, ?.C, ?.D, ?.I, ?.R, ?.S and ?.Type: GrantFiled: February 20, 2014Date of Patent: August 27, 2019Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Pierre-Emmanuel Julien Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli
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Patent number: 10380309Abstract: We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in principle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality.Type: GrantFiled: June 1, 2015Date of Patent: August 13, 2019Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni De Micheli
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Patent number: 10348306Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.Type: GrantFiled: March 9, 2018Date of Patent: July 9, 2019Assignees: University of Utah Research Foundation, Ecole Polytechnique Federale de Lausanne (EPFL)Inventors: Pierre-Emanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli, Edouard Giacomin
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Publication number: 20180262197Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.Type: ApplicationFiled: March 9, 2018Publication date: September 13, 2018Inventors: Pierre-Emanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli, Edouard Giacomin
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Patent number: 9971862Abstract: A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1?i?k, connects to one of the inputs of routing multiplexers of LUTj, i<j?k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2?m?k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2?p?k+1, p?1 inputs of the LUTp are connected to the outputs of LUTq, 1?q?j, by means of fast interconnections; and (c) a cluster-based logic block contains at least oneType: GrantFiled: July 24, 2015Date of Patent: May 15, 2018Assignee: Ecole Polytechnique Fédérale de Lausanne (EPFL)Inventors: Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni De Micheli
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Publication number: 20170177750Abstract: A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ?. The method further comprises providing a commutativity, a majority (?.M), an associativity (?.A), a distributivity (?.D), an inverter propagation (?.I), a relevance (?.R), a complementary associativity (?.C), and a substitution (?.S) transformation; and combining the ?.M, ?.C, ?.A, ?.D, ?.I, ?.R, ?.C and ?.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the ?.A, ?.C, ?.D, ?.I, ?.R, ?.S and ?.Type: ApplicationFiled: February 20, 2014Publication date: June 22, 2017Inventors: Pierre-Emmanuel Julien Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli
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Patent number: 9685959Abstract: A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop.Type: GrantFiled: September 11, 2015Date of Patent: June 20, 2017Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Luca Gaetano Amarú, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni De Micheli
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Publication number: 20160350469Abstract: We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in principle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality.Type: ApplicationFiled: June 1, 2015Publication date: December 1, 2016Inventors: Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc GAILLARDON, Giovanni DE MICHELI
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Publication number: 20160322101Abstract: A bipolar resistive switching device including an electrically conductive bottom electrode, a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack including: at least one MOx layer, at least one oxygen gettering layer NOy, wherein the resistive switching device further includes an electrically conductive top electrode.Type: ApplicationFiled: June 24, 2016Publication date: November 3, 2016Inventors: Davide Sacchetto, Shashi Kanth Bobba, Pierre-Emmanuel Julien Marc Gaillardon, Yusuf Leblebici, Giovanni De Micheli, Tugba Demirci
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Patent number: 9412940Abstract: A bipolar resistive switching device (RSM device, FIG. 35) comprises an electrically conductive bottom electrode (BE, FIG. 35); a stack of transition metal oxides layers (RSM, FIG. 35), a number of transition metal oxide layers (RSO, FIG. 35) being equal or greater than 2, the stack comprising: at least one MOx layer (RSOA, FIG. 35), at least one oxygen gettering layer NOy (RSOB, FIG. 35). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG. 35).Type: GrantFiled: July 19, 2013Date of Patent: August 9, 2016Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Davide Sacchetto, Shashi Kanth Bobba, Pierre-Emmanuel Julien Marc Gaillardon, Yusuf Leblebici, Giovanni De Micheli, Tugba Demirci
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Publication number: 20160077154Abstract: A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop.Type: ApplicationFiled: September 11, 2015Publication date: March 17, 2016Inventors: Luca Gaetano AMARÚ, Pierre-Emmanuel Julien Marc GAILLARDON, Giovanni DE MICHELI
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Publication number: 20160063168Abstract: A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1?i?k, connects to one of the inputs of routing multiplexers of LUTj, i<j?k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2?m?k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2?p?k+1, p?1 inputs of the LUTp are connected to the outputs of LUTq, 1?q?j, by means of fast interconnections; and (c) a cluster-based logic block contains at least oneType: ApplicationFiled: July 24, 2015Publication date: March 3, 2016Inventors: Xifan TANG, Pierre-Emmanuel Julien Marc GAILLARDON, Giovanni DE MICHELI
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Patent number: 9276573Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.Type: GrantFiled: July 28, 2014Date of Patent: March 1, 2016Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNEInventors: Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli
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Patent number: 9252252Abstract: This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.Type: GrantFiled: May 22, 2013Date of Patent: February 2, 2016Assignee: ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)Inventors: Giovanni De Micheli, Yusuf Leblebici, Michele De Marchi, Davide Sacchetto
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Publication number: 20160028396Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.Type: ApplicationFiled: July 28, 2014Publication date: January 28, 2016Inventors: Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli
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Patent number: 9130568Abstract: A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.Type: GrantFiled: August 7, 2013Date of Patent: September 8, 2015Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Luca Gaetano Amaru, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni De Micheli
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Publication number: 20150200363Abstract: A bipolar resistive switching device (RSM device, FIG. 35) comprises an electrically conductive bottom electrode (BE, FIG. 35); a stack of transition metal oxides layers (RSM, FIG. 35), a number of transition metal oxide layers (RSO, FIG. 35) being equal or greater than 2, the stack comprising: at least one MOx layer (RSOA, FIG. 35), at least one oxygen gettering layer NOy (RSOB, FIG. 35). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG. 35).Type: ApplicationFiled: July 19, 2013Publication date: July 16, 2015Inventors: Davide Sacchetto, Shashi Kanth Bobba, Pierre-Emmanuel Julien Marc Gaillardon, Yusuf Leblebici, Giovanni De Micheli, Tugba Demirci
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Publication number: 20140043060Abstract: A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.Type: ApplicationFiled: August 7, 2013Publication date: February 13, 2014Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Luca Gaetano AMARU, Pierre-Emmanuel Julien Marc GAILLARDON, Giovanni DE MICHELI
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Publication number: 20130313524Abstract: This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.Type: ApplicationFiled: May 22, 2013Publication date: November 28, 2013Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Giovanni De Micheli, Yusuf Leblebici, Michele De Marchi, Davide Sacchetto
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Patent number: 8042087Abstract: A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connType: GrantFiled: October 10, 2007Date of Patent: October 18, 2011Assignee: Ecole Polytechnique Federale De Lausanne (EPFL)Inventors: Srinivasan Murali, Luca Benini, Giovanni De Micheli