Abstract: A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.

Abstract: A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.

Abstract: The aim of the present invention is a method to achieve the customization of the communication network of a multicore communication system. This goal is achieved thanks to a method to design a multicore communication system, said communication system comprising a communication network having a plurality of switches and several elements communicating through the communication network, said method comprising the steps of: a) defining the communication network topology, comprising a number of switches, the architecture of said switches and the interconnection between said switches, b) defining routes to communicate among the elements through the switches according to the application running on the system, c) marking the input-to-output connections used within the switches traversed by these routes, d) removing all or part of the electronic components related to the non-marked connections.

Abstract: A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically conn

Abstract: One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemented in hardware or mixed hardware/software systems are making use of complex data structures stored in one or multiple memories. As a result, many of the C/C++ features which were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation/deallocation and pointers used to manage data. This inventors present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. This solution fits current memory management methodologies. It consists of instantiating a hardware allocator tailored to an application and a memory architecture. This work also supports the resolution of pointers without restriction on the data structures.