Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.

Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.

Abstract: Methods and apparatus for efficiently servicing isochronous streams (such as media data streams) associated with a network. In one embodiment, an Isochronous Cycle Manager (ICM), receives multiple independent streams of packets that include isochronous packets arriving according to different time bases (e.g., where each stream has a different time base). The packets are sorted by the ICM into a buffering mechanism according to their required presentation time. Additionally the ICM calculates a launch time for each packet. The NIC transmits the packets from the queue according to an access scheme, such as a time division multiplexed (TDM) scheme where each of a plurality of cycles is subdivided into time slots. During appropriate time slots, the NIC transmits the packets in chronological order, as read out of the buffering mechanism.

Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.

Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.

Abstract: A method for automatically producing a video and audio mix at a first portable electronic device. The method receives a request to capture video and audio, performs a network discovery process to find a second portable electronic device, and sends a message to the second device indicating when to start recording audio for a double system recording session. The method initiates the recording session, such that both devices record concurrently. In response to the first device stopping the recording of audio and sound, signaling the second device to stop recording for the identified recording session. In response to the first device receiving a first audio track from the second device that contains an audio signal recorded during the recording session, automatically generating a mix of video and audio, such that one of the audio signals from the first and second tracks is ducked relative to the other.

Abstract: An analog to digital conversion circuit receives a transducer output signal and outputs a data bitstream, where a latch or flip flop has an input that receives a clock signal. An AC-DC power converter receives the clock signal and produces a DC voltage which may power the analog to digital conversion circuit. The AC-DC power converter has a rectifier, an energy store and a voltage regulator, charge pump or filter, which draws power from the energy store to produce the DC voltage. A control circuit delays replenishment of the energy store by the rectified clock signal, responsive to the clock signal. Other embodiments are also described and claimed.

Abstract: A method for automatically producing a video and audio mix at a first portable electronic device. The method receives a request to capture video and audio, performs a network discovery process to find a second portable electronic device, and sends a message to the second device indicating when to start recording audio for a double system recording session. The method initiates the recording session, such that both devices record concurrently. In response to the first device stopping the recording of audio and sound, signaling the second device to stop recording for the identified recording session. In response to the first device receiving a first audio track from the second device that contains an audio signal recorded during the recording session, automatically generating a mix of video and audio, such that one of the audio signals from the first and second tracks is ducked relative to the other.

Abstract: An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0, 1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed.

Abstract: An analog to digital conversion circuit receives a transducer output signal and outputs a data bitstream, where a latch or flip flop has an input that receives a clock signal. An AC-DC power converter receives the clock signal and produces a DC voltage which may power the analog to digital conversion circuit. The AC-DC power converter has a rectifier, an energy store and a voltage regulator, charge pump or filter, which draws power from the energy store to produce the DC voltage. A control circuit delays replenishment of the energy store by the rectified clock signal, responsive to the clock signal. Other embodiments are also described and claimed.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: A method for audio signal processing, where an audio amplifier drives a load through a connector, using 1) an input audio signal, and 2) a signal from a return pin of the connector. Output headroom of the audio amplifier is automatically detected, while the amplifier is driving the load. A variable resistor circuit that is coupled to provide variable resistance between the return pin of the connector and a ground plane, is automatically adjusted, in response to the detected output headroom of the amplifier. Other embodiments are also described and claimed.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: A multi-channel audio system that can provide a variable sub-sample delay between two or more audio channels. In one embodiment, a variable timing clock generator generates multiple clock signals where each may have different phase, and the clock generator can vary the phase difference, in accordance with a sub-sample delay setting input. These clock signals are used by respective digital-to-analog converters (DACs) to convert the digital audio channels into analog form. In another embodiment, a variable delay block is added to an oversampling DAC, on a per channel basis. Other embodiments are also described and claimed.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract: A system for verifying clock synchronization between master and slave network equipment is provided. The master includes a transmitter, first control logic, and a first processor. The slave includes a receiver, second control logic, and a second processor. The transmitter may send synchronization packets to the receiver. When a synchronization packet is sent, the first control logic forwards a first timestamp sample to the first processor. In response to receiving a synchronization packet, the receiver may generate a second timestamp sample that is forwarded to the second processor. When a number of first timestamp samples are collected at the first processor, the transmitter may send a timestamp packet to the receiver. In response to receiving the timestamp packet, the receiver may compare the first and second timestamp samples in an effort to synchronize a slave reference clock in the slave to a master reference clock in the master.

Abstract: A method for audio signal processing, where an audio amplifier drives a load through a connector, using 1) an input audio signal, and 2) a signal from a return pin of the connector. Output headroom of the audio amplifier is automatically detected, while the amplifier is driving the load. A variable resistor circuit that is coupled to provide variable resistance between the return pin of the connector and a ground plane, is automatically adjusted, in response to the detected output headroom of the amplifier. Other embodiments are also described and claimed.

Abstract: Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.

Abstract: Methods and apparatus for efficiently servicing isochronous streams (such as media data streams) associated with a network. In one embodiment, an Isochronous Cycle Manager (ICM), receives multiple independent streams of packets that include isochronous packets arriving according to different time bases (e.g., where each stream has a different time base). The packets are sorted by the ICM into a buffering mechanism according to their required presentation time. Additionally the ICM calculates a launch time for each packet. The NIC transmits the packets from the queue according to an access scheme, such as a time division multiplexed (TDM) scheme where each of a plurality of cycles is subdivided into time slots. During appropriate time slots, the NIC transmits the packets in chronological order, as read out of the buffering mechanism.