Patents by Inventor Gireesh Rajendran

Gireesh Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160380592
    Abstract: Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Ashish Lachhwani
  • Publication number: 20160373062
    Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Ayush Mittal, Gireesh Rajendran, Rahul Karmaker
  • Publication number: 20160294327
    Abstract: A method and apparatus for linearizing a baseband filter are provided. The apparatus is configured to, via a first conducting module, receive a first current signal. The apparatus is further configured to, via a converting module, receive a second current signal, generate a voltage signal based on the second current signal, and apply the voltage signal to the first conducting module. An amount of the second current signal received by the converting module is based on an amount of the first current signal flowing through the first conducting module. The apparatus is also configured to, via a second conducting module, control an output current signal based on the voltage signal. The output current signal is controlled to be a linear replica of the first current signal for in-band frequencies.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 6, 2016
    Inventors: Bhushan Shanti ASURI, Alok Prakash JOSHI, Gireesh RAJENDRAN
  • Publication number: 20160234876
    Abstract: One aspect of an apparatus for wireless communications is disclosed. The apparatus includes a controller, a first transceiver, and a second transceiver. The first transceiver is configurable by the controller to support first communications through a cellular network to at least one of a packet-based network and a circuit-switched network. The second transceiver configurable by the controller to operate with the first transceiver to support first communications through the cellular network in a first mode and support second communications through an access point to the packet-based network in a second mode. In an aspect, the second transceiver is further configured to switch from the first mode to the second mode by moving its wireless connection from the cellular network to the access point while maintaining a network-layer connection to the cellular network.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventors: Gangadhar BURRA, MeeLan LEE, Gireesh RAJENDRAN, Anup SAVLA, Jeremy LIN, Soumya DAS, Bongyong SONG
  • Publication number: 20160226488
    Abstract: Disclosed is circuitry for operating a switch which sees high voltage swings across its source, gate, drain, and bulk terminals. The circuitry generates one or more bias voltages in proportion to an input voltage swing. The one or more bias voltages may be used to bias the gate and bulk terminals to provide reliable and improved turn OFF performance in the switch.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9385901
    Abstract: A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gireesh Rajendran, Gurkanwal Singh Sahota, Rakesh Kumar
  • Publication number: 20160142231
    Abstract: A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 19, 2016
    Inventors: Gireesh Rajendran, Gurkanwal Singh Sahota, Rakesh Kumar
  • Publication number: 20160126895
    Abstract: An I converter outputs I sign data and I magnitude data based on received I data. A Q converter outputs Q sign data and Q magnitude data based on received Q data. An I clock generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator generates an I magnitude pulse stream based on the I magnitude data. A Q modulator generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier generates an amplified signal based on the output signal.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 5, 2016
    Inventors: Gireesh Rajendran, Rakesh Kumar, Alok Prakask Joshi, Subhashish Mukherjee, Krishnaswamy Thiagarajan, Apu Sivadas
  • Publication number: 20160112006
    Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 21, 2016
    Applicant: Texas Instruments Incorporated
    Inventors: Gireesh Rajendran, Rakesh Kumar, Subhashish Mukherjee, Ashish Lachhwani
  • Publication number: 20160103460
    Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: Abhishek Agrawal, Yogesh Darwhekar, Gireesh Rajendran
  • Publication number: 20160079946
    Abstract: An apparatus includes a first transistor configured to amplify first signal components within a first frequency band of a radio frequency signal, a second transistor configured to amplify second signal components within a second frequency band of the radio frequency signal, and a third transistor configured to amplify third signal components within a third frequency band of the radio frequency signal. The apparatus also includes a degeneration inductor having a first tapping point, a second tapping point, and a third tapping point. The first tapping point is coupled to the first transistor, the second tapping point is coupled to the second transistor, and the third tapping point is coupled to the third transistor.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Gireesh Rajendran, Rakesh Kumar, Manohar Seetharam
  • Patent number: 9246552
    Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
    Type: Grant
    Filed: June 28, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhishek Agrawal, Yogesh Darwhekar, Gireesh Rajendran
  • Patent number: 9160309
    Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 13, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Gireesh Rajendran, Rakesh Kumar, Vinod Venugopal Panikkath, Ayush Mittal, Alok Joshi
  • Patent number: 9083075
    Abstract: A device includes multiple transceivers, a coupling block and an antenna. The transceivers operate according to time-division multiple access (TDMA) techniques. The coupling block is designed to enable the multiple transceivers to transmit or receive corresponding signals using the antenna. The multiple transceivers include a first transmitter and a second transmitter. The first transmitter is connected to the antenna via a first coupling network. The second transmitter is connected to the antenna via a series connection of a second coupling network and at least a portion of the first coupling network. Other transmitters are connected to the antenna via a series arrangement of at least a portion of the first coupling network and corresponding coupling networks.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 14, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Apu Sivadas
  • Publication number: 20150194944
    Abstract: Exemplary embodiments are related to wideband matching devices. A device may include a primary winding including a first plurality of inductors in series and a first switch coupled to the primary winding and configured to tune the primary winding to a frequency band of a plurality of frequency bands. The device may also include a secondary winding including a second plurality of inductors in series and a second switch coupled to the secondary winding and configured to tune the secondary winding to the frequency band.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Alok Joshi, Gireesh Rajendran, Apu Sivadas
  • Publication number: 20150162895
    Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Gireesh Rajendran, Rakesh Kumar, Vinod Venugopal Panikkath, Ayush Mittal, Alok Joshi
  • Publication number: 20150091502
    Abstract: A method of coupling a first port of a single antenna to a first coupling circuit and a second port of the single antenna to a second coupling circuit. The method includes coupling a wireless charging unit to the first coupling unit and coupling an NFC transceiver block to the second coupling circuit. The method further includes isolating the single antenna from the wireless charging unit during a time interval when the NFC transceiver block is operational and isolating the single antenna from the NFC transceiver block during a time interval when the wireless charging unit is operational.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Subhashish Mukherjee, Yogesh Darwhekar, Gireesh Rajendran
  • Patent number: 8975961
    Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20150004909
    Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path, A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
    Type: Application
    Filed: June 28, 2014
    Publication date: January 1, 2015
    Inventors: Abhishek Agrawal, Yogesh Darwhekar, Gireesh Rajendran
  • Publication number: 20140347124
    Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran