Patents by Inventor Giridhar Nallapati
Giridhar Nallapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9245971Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.Type: GrantFiled: September 27, 2013Date of Patent: January 26, 2016Assignee: QUALCOMM IncorporatedInventors: Bin Yang, P R Chidambaram, John Jianhong Zhu, Jihong Choi, Da Yang, Ravi Mahendra Todi, Giridhar Nallapati, Chock Hing Gan, Ming Cai, Samit Sengupta
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Publication number: 20150303145Abstract: The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit.Type: ApplicationFiled: April 17, 2014Publication date: October 22, 2015Applicant: QUALCOMM IncorporatedInventors: John Jianhong ZHU, PR CHIDAMBARAM, Giridhar NALLAPATI, Choh Fei YEAP
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Patent number: 9070551Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: GrantFiled: August 23, 2013Date of Patent: June 30, 2015Assignee: Qualcomm IncorporatedInventors: Benjamin John Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock H. Gan, Giridhar Nallapati, Matthew D. Youngblood, William R. Flederbach
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Patent number: 9024418Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.Type: GrantFiled: March 14, 2013Date of Patent: May 5, 2015Assignee: QUALCOMM IncorporatedInventors: John Jianhong Zhu, Giridhar Nallapati, PR Chidambaram
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Publication number: 20150091060Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: QUALCOMM IncorporatedInventors: Bin Yang, PR Chidambaram, John Jianhong Zhu, Jihong Choi, Da Yang, Ravi Mahendra Todi, Giridhar Nallapati, Chock Hing Gan, Ming Cai, Samit Sengupta
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Publication number: 20150064864Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: ApplicationFiled: November 11, 2014Publication date: March 5, 2015Inventors: Benjamin John BOWERS, James W. HAYWARD, Charanya GOPAL, Gregory Christopher BURDA, Robert J. BUCKI, Chock H. GAN, Giridhar NALLAPATI, Matthew D. YOUNGBLOOD, William R. FLEDERBACH
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Publication number: 20140367760Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: ApplicationFiled: August 23, 2013Publication date: December 18, 2014Applicant: Qualcomm IncorporatedInventors: Benjamin John BOWERS, James W. HAYWARD, Charanya GOPAL, Gregory Christopher BURDA, Robert J. BUCKI, Chock H. GAN, Giridhar NALLAPATI, Matthew D. YOUNGBLOOD, William R. FLEDERBACH
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Publication number: 20140264629Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: John J. Zhu, Giridhar Nallapati, Chidi Chidambaram
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Patent number: 8836040Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.Type: GrantFiled: November 7, 2012Date of Patent: September 16, 2014Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati, Animesh Datta
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Publication number: 20140225223Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.Type: ApplicationFiled: February 12, 2013Publication date: August 14, 2014Applicant: QUALCOMM INCORPORATEDInventors: John J. Zhu, PR Chidambaram, Giridhar Nallapati, Choh fei Yeap
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Publication number: 20140225224Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.Type: ApplicationFiled: February 12, 2013Publication date: August 14, 2014Applicant: QUALCOMM INCORPORATEDInventors: John J. Zhu, PR Chidambaram, Giridhar Nallapati, Choh fei Yeap
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Publication number: 20140197520Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, Bin Yang, Giridhar Nallapati, PR Chidambaram
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Patent number: 8782576Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: GrantFiled: August 26, 2013Date of Patent: July 15, 2014Assignee: QUALCOMM IncorporatedInventors: Benjamin John Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock H. Gan, Giridhar Nallapati, Matthew D. Youngblood, William R. Flederbach
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Publication number: 20140124868Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: QUALCOMM IncorporatedInventors: Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati, Animesh Datta