Patents by Inventor Girolamo Gallo
Girolamo Gallo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7940575Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.Type: GrantFiled: March 28, 2008Date of Patent: May 10, 2011Assignee: QIMONDA AGInventors: Roberto Ravasio, Andreas Kux, Detlev Richter, Girolamo Gallo, Josef Willer, Ramirez Xavier Veredas
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Patent number: 7800943Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided.Type: GrantFiled: January 18, 2008Date of Patent: September 21, 2010Assignee: Qimonda AGInventors: Roberto Ravasio, Detlev Richter, Gert Koebernik, Girolamo Gallo, Mirko Reissmann, Ramirez Xavier Veredas
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Patent number: 7701776Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: GrantFiled: September 22, 2008Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio G. Marotta
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Patent number: 7635991Abstract: Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.Type: GrantFiled: May 2, 2006Date of Patent: December 22, 2009Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio Marotta, Giovanni Naso
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Publication number: 20090244949Abstract: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: Roberto Ravasio, Andreas Kux, Detlev Richter, Girolamo Gallo, Josef Willer, Ramirez Xavier Veredas
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Publication number: 20090185425Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Inventors: Roberto Ravasio, Detlev Richter, Gert Koebernik, Girolamo Gallo, Mirko Reissmann, Ramirez Xavier Veredas
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Publication number: 20090040821Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: ApplicationFiled: September 22, 2008Publication date: February 12, 2009Inventors: Girolamo Gallo, Giulio G. Marotta
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Patent number: 7440332Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: GrantFiled: December 18, 2007Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio G. Marotta
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Publication number: 20080094909Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: ApplicationFiled: December 18, 2007Publication date: April 24, 2008Inventors: Girolamo Gallo, Giulio Marotta
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Patent number: 7324381Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: GrantFiled: May 3, 2006Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio G. Marotta
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Publication number: 20070253255Abstract: A memory device, a method for sensing a current output and a sensing circuit are disclosed. In one embodiment, a first voltage is supplied at least to a drain and a source terminal of a neighboring memory cell before sensing, and the first voltage is applied to a source terminal of a selected memory cell, while sensing the current though the selected memory cell.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Inventors: Girolamo Gallo, Giorgio Oddone, Alberto Taddeo, Carmelo Giunta, Marco Carminati
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Patent number: 7271620Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.Type: GrantFiled: November 17, 2006Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio Marotta
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Patent number: 7206240Abstract: Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.Type: GrantFiled: February 25, 2004Date of Patent: April 17, 2007Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Tommaso Vali, Giulio Giuseppe Marotta
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Publication number: 20070063730Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.Type: ApplicationFiled: November 17, 2006Publication date: March 22, 2007Inventors: Girolamo Gallo, Giulio Marotta
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Patent number: 7164607Abstract: Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.Type: GrantFiled: June 1, 2005Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giuliano Gennaro Imondi, Giovanni Naso, Tommaso Vali
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Patent number: 7161376Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.Type: GrantFiled: February 21, 2006Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio Marotta
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Publication number: 20070002630Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.Type: ApplicationFiled: May 3, 2006Publication date: January 4, 2007Inventors: Girolamo Gallo, Giulio Marotta
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Publication number: 20060261853Abstract: Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.Type: ApplicationFiled: May 2, 2006Publication date: November 23, 2006Inventors: Girolamo Gallo, Giulio Marotta, Giovanni Naso
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Publication number: 20060139051Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.Type: ApplicationFiled: February 21, 2006Publication date: June 29, 2006Inventors: Girolamo Gallo, Giulio Marotta
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Patent number: 7064582Abstract: Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.Type: GrantFiled: November 4, 2003Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventors: Girolamo Gallo, Giulio Marotta, Giovanni Naso