Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.

Abstract: A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The resulting architecture effectively doubles throughput without increasing memory device latency.

Abstract: Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.

Abstract: Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.

Abstract: A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The invention effectively doubles throughput without increasing memory device latency.

Abstract: Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.

Abstract: A method for speeding up the convergence of the back-propagation algorithm applied to realize the learning process in a neural network of the multilayer perceptron type intended for instance to recognize a set of samples. The method comprises a first stage based upon the elementary concept of progressively increasing the capability for learning of the network by progressively adding new samples as they are recognized by the network to a starting set of learning samples; a second stage based upon the concept of progressively increasing the learning capabilities of the network by progressively adding not previously recognized samples; and a third stage based upon the concept of progressively increasing the learning capabilities of the network by progressive corruption in the meaning of the assimilation between recognized samples and not recognized samples and their subsequent exposure to the network.

Abstract: A method and apparatus for recognizing a script written character wherein the character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological and vector features of the character are extracted from the character, then the topological and vector features of the character are compared with topological and vector features of a plurality of reference characters defining a set of reference characters stored in a memory. Each of the reference characters included in the set corresponds to a specific script written character. A logic process is then performed to determine which reference character of the set of reference characters has topological and vector features most closely corresponding to the topological and vector features of the digitized character thereby identifying the script written character.

Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering device and digitised by appropriate device. The digitised character is then stored in, for example, a memory. Codes representing topological, vector dimension features and the microfeatures of the character are extracted from the character, then the features of the character are compared with a set of reference features corresponding thereto stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character. The relative weighting of the feature can be varied for different types of script or confusing characters to enable still more accurate recognition.

Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological features of the character are extracted from the character, then the topological features of the character are compared with a set of reference topological features stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character.