Patents by Inventor Giuseppe Arena

Giuseppe Arena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process
    Patent number: 6888213
    Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Roberto Modica, Giuseppe Arena
  • Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process
    Publication number: 20040026761
    Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.
    Type: Application
    Filed: May 22, 2003
    Publication date: February 12, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Roberto Modica, Giuseppe Arena
  • Method for manufacturing a SOI wafer
    Patent number: 6506658
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 14, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri
  • Method for manufacturing a SOI wafer
    Publication number: 20010023094
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Application
    Filed: December 29, 2000
    Publication date: September 20, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri