Abstract: Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.

Abstract: A memory device comprises a memory array and a memory control unit. The memory includes multi-level memory cells. The memory control unit is configured to: initiate programming of memory cells of the memory array using a first pass programming operation, wherein the first pass programming operation places programming data using a first and second voltage threshold distributions; read programmed memory cells using a first read voltage level on word lines of the memory cells; read the programmed memory cells using a second read voltage level on the word lines of the memory cells; determine a number of the programmed memory cells with a voltage threshold placed between the first and second voltage threshold distributions by the programming; and suspend second pass programming of the memory cells in response to the determined number of cells exceeding a specified threshold number, and initiate a second pass programming operation otherwise.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A controller can receive an operation. Here the operation includes address data with a logical address portion and a physical address portion. The controller can then extract an index value and a location value from the physical address portion. The controller can retrieve a key using the index value and invoke a reversible function—using the index value and the location value—to produce a physical address. The controller can then perform the operation using the physical address.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

Abstract: A memory device comprises a memory array and a memory control unit. The memory includes multi-level memory cells. The memory control unit is configured to: initiate programming of memory cells of the memory array using a first pass programming operation, wherein the first pass programming operation places programming data using a first and second voltage threshold distributions; read programmed memory cells using a first read voltage level on word lines of the memory cells; read the programmed memory cells using a second read voltage level on the word lines of the memory cells; determine a number of the programmed memory cells with a voltage threshold placed between the first and second voltage threshold distributions by the programming; and suspend second pass programming of the memory cells in response to the determined number of cells exceeding a specified threshold number, and initiate a second pass programming operation otherwise.

Abstract: Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A controller can receive an operation. Here, the operation includes address data with a logical address portion and a physical address portion. The controller can then extract an index value and a location value from the physical address portion. The controller can retrieve a key using the index value and invoke a reversible function—using the index value and the location value—to produce a physical address. The controller can then perform the operation using the physical address.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.